MAX7370 Maxim, MAX7370 Datasheet - Page 12

• Manufacturer Part Number: MAX7370
• Description: The MAX7370 I²C-interfaced peripheral provides microprocessors with management of up to 64 key switches, with optional GPIO and PWM-controlled LED drivers
• Manufacturer: Maxim

with I
These registers configure the pin as an open-drain
or push-pull output. GPO Output Mode 1 register bits
D[7:0] correspond with ROW7–ROW0. See
GPO Output Mode 2 register bits D[7:0] correspond with
COL7–COL0. See
0 to configure the output mode as open-drain and 1 to
configure the output mode as push-pull.
These registers configure input and output voltages to
be referenced to V
register bits D[7:0] correspond with ROW7–ROW0. See
Table
respond with COL7–COL0. See
for input/output voltages referenced to V
to 1 for the input/output voltage referenced to V
The GPIO Values 1 and 2 registers contain the debounced
input data for all the GPIOs for ROW7–ROW0 and COL7–
COL0, respectively. See
debounce period delay prior to detecting a transition on
the input port. This prevents a false interrupt from occur-
ring when changing a port from an output to an input. The
GPIO Values 1 and 2 registers report the state of all input
ports regardless of any interrupt mask settings.
When writing to the GPIO Values 1 and 2 registers, the
corresponding port voltage is set high when written 1 or
cleared when written 0. Reading the port when config-
ured as an output always returns the value 0 for the cor-
responding port regardless of the output value.
Enabling bit D_ in this register enables the direct level
shifter between GPIO pins COL_ and ROW_. See
Table
enables level shifting between COL5 and ROW5. The
direction of the level shifter is controlled by the GPIO
Direction 2 register (0x35). When setting the correspond-
ing bit in the GPIO Direction 2 register to 0, COL_ are
inputs, and ROW_ are outputs. When setting the bit to 1,
ROW_ become inputs and COL_ become outputs.
The GPIO Global Configuration register controls the main
settings for the GPIO ports. See
8 x 8 Key-Switch Controller and LED Driver/GPIOs
GPO Output Mode 1 and 2 Registers (0x36, 0x37)
19. GPIO Supply Voltage 2 register bits D[7:0] cor-
23. As an example, setting D5 to logic-high
GPIO Values 1 and 2 Registers (0x3A, 0x3B)
GPIO Global Configuration Register (0x40)
GPIO Level-Shifter Enable Register (0x3C)
2
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Table
CC
or V
18. Set the corresponding bit to
Tables 21
GPIO Supply Voltage 1 and 2
LA
. GPIO Supply Voltage 1
Table
Table
Registers (0x38, 0x39)
and 22. There is one
20. Set the bit to 0
24. Bit D5 enables
CC
or set the bit
Table
LA
.
17.
interrupt generation for I
enable/shutdown bit for the GPIOs. Bit D3 functions as a
software reset for the GPIO registers (0x31 to 0x5B). Bits
D[2:0] set the fade-in/out time for the LED drivers.
The GPIO Debounce Configuration Register sets the
amount of time a GPIO must be held in order for the
device to register a logic transition. See
GPIO debounce setting is independent of the key-switch
debounce setting. Five bits (D[4:0]) set 32 possible
debounce times from 9ms up to 40ms.
The LED Constant-Current Setting register sets the global
constant-current amount. See
the global current values between 10mA and 20mA.
This setting only applies to the LED driver-enabled pins,
COL7–COL4.
The Common PWM Ratio register stores the common
constant-current output PWM duty cycle. See
The values stored in this register translate over to a PWM
ratio in the same manner as the individual PWM ratio reg-
isters (0x50 to 0x53). Ports can use their own individual
PWM value or the common PWM value. Write to this reg-
ister to change the PWM ratio of several ports at once.
The I
(D0) that indicates if an I
Table
initiated interrupt.
Each LED driver port has an individual PWM ratio register,
0x50 to 0x53. See
these registers to configure the number of cycles out of
256 the output sinks current (LED is on), from 0 cycles to
254 cycles. Use 0xFF to have an output continuously sink
current (always on). For applications requiring multiple
ports to have the same intensity, program a particular
port’s configuration register (0x54 to 0x57) to use the
Common PWM Ratio register (0x45). New PWM settings
take place at the beginning of a PWM cycle, to allow
changes from common intensity to individual intensity with
no interruption in the PWM cycle.
2
C Timeout Flag register contains a single bit
28. Read this register to clear an I
GPIO Debounce Configuration Register (0x42)
LED Constant-Current Setting Register (0x43)
I
2
C Timeout Flag Register (0x48) (Read Only)
Common PWM Ratio Register (0x45)
Table
COL4–COL7 Individual PWM Ratio
29. Use values 0x00 to 0xFE in
2
2
C timeout has occurred. See
C timeouts. D4 is the main
Registers (0x50 to 0x53)
Table
MAX7370
26. Bit D0 selects
Table
2
C timeout-
Table
25. The
27.