EL4581CSZ-T7 Intersil, EL4581CSZ-T7 Datasheet - Page 7

• Manufacturer Part Number: EL4581CSZ-T7
• Description: IC VIDEO SYNC SEPARATOR 8-SOIC
• Manufacturer: Intersil
• Type: Synchronous Separatorr

Specifications of EL4581CSZ-T7

• Applications: Displays, Test Equipment, Video
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: EL4581CSZ-T7; EL4581CSZ-T7TR

Description of Operation
A simplified block diagram is shown in Figure 13. The
following description is intended to provide the user with
sufficient information to be able to understand the effects
that the external components and signal conditions have on
the outputs of the integrated circuit.
The video signal is AC coupled to pin 2 via the capacitor C
nominally 0.1µF. The clamp circuit A1 will prevent the input
signal on pin 2 going any more negative than 1.5V, the value
of reference voltage V
negative part of the video waveform, will be clamped at 1.5V.
The current source I
capacitor during the remaining portion of the H line,
approximately 58µs for a 15.75kHz timebase. From I•t = C•V,
the video time-constant can be calculated. It is important to
note that the charge taken from the capacitor during video
must be replaced during the sync tip time, which is much
shorter, (ratio of x12.5). The corresponding current to restore
the charge during sync will therefore be an order of
magnitude higher, and any resistance in series with C
cause sync tip crushing. For this reason, the internal series
resistance has been minimized and external high resistance
values in series with the input coupling capacitor should be
avoided. The user can exercise some control over the value
of the input time constant by introducing an external pull-up
resistance from pin 2 to the 5V supply. The maximum
voltage across the resistance will be V
1
, nominally 10µA, charges the coupling
R1
0.5V TO 2V
DYNAMIC
. Thus the sync tip, the most
RANGE
COMPOSITE SYNC OUTPUT, PIN 1
INPUT
BACK PORCH OUTPUT, PIN 5
7
50%
t
CS
DD
FIGURE 12. STANDARD (NTSC INPUT) H. SYNC DETAIL
less 1.5V, for black
SYNC LEVEL
t
BD
COLOR BURST
SYNC TIP
1
40 IRE
will
1
V
DEPENDS ON WIDTH OF INPUT SYNC AT 50% POINTS
,
EL4581
CLAMP
t
B
level. For a net discharge current greater than zero, the
resistance should be greater than 450k. This will have the
effect of increasing the time constant and reducing the
degree of picture tilt. The current source I
reference current I
adjustment, as explained later.
The signal is processed through an active 3-pole filter (F1)
designed for minimum ripple with constant phase delay. The
filter attenuates the color burst by 24dB and eliminates fast
transient spikes without sync crushing. An external filter is
not necessary. The filter also amplifies the video signal by
6dB to improve the detection accuracy. Note that the filter
cut-off frequency is a function of R
proportional to I
Internal reference voltages (block V
to supply voltage variation are derived on the chip.
Reference V
voltage of 1.7V nominal. Consequently, it can be seen that
the external resistance R
reference current I
about 6kΩ, much less than R
functions on the chip are referenced to I
excellent supply voltage rejection.
Comparator C2 on the input to the sample and hold block
(S/H) compares the leading and trailing edges of the sync
pulse with a threshold voltage V
V
SLICE
WHITE LEVEL
BLACK LEVEL
R4
BLANKING LEVEL
OT
with op amp A2 forces pin 6 to a reference
.
TR
TR
. The internal resistance R
and thus increases with scan rate
SET
SET
will determine the value of the
R2
. All the internal timing
100 IRE
40 IRE
SET
VIDEO
, which is referenced at a
SYNC
REF
through I
) with high immunity
TR
1
directly tracks
and have
November 12, 2010
3
OT
is only
and is
FN7172.2