ISL59885ISZ Intersil, ISL59885ISZ Datasheet - Page 11

• Manufacturer Part Number: ISL59885ISZ
• Description: IC SEPARATOR VID SYNC AUTO 8SOIC
• Manufacturer: Intersil
• Type: Synchronous Separatorr

Specifications of ISL59885ISZ

• Applications: HD Video
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Applications Information
Video In
Refer to the “Simplified Block Diagram” on page 12.
An AC coupled video signal is input to Video In pin 2 via C
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about 1mA.
A clamp discharge current of about 10µA is always
attempting to discharge C
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from IT = CV, where V is the droop voltage, I is the discharge
current, t is the time between sync pulses (sync period-sync
tip width), and C is C
An NTSC video signal has a horizontal frequency of
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time t = 58.9µs. The droop voltage will then
be V = 5.9mV. This is less than 2% of a nominal sync tip
amplitude of 286mV. The charge represented by this droop
is replaced in a time given by t = CV/I, where I = clamp
charge current = 5.3mA. Here t = 590ns, about 12% of the
sync pulse width of 4.7µs. It is important to choose C
enough so that the droop voltage does not approach the
switching threshold of the internal comparator.
Composite Sync
The Composite Sync output is simply a reproduction of the
input signal with the active video removed. The sync tip of
the Composite video signal is clamped to 1.5V at pin 2 and
then slices at 70mV above the sync tip reference. The output
signal is buffered out to pin 1. When loss of sync, the
Composite Sync output is held low.
Vertical Sync
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the ISL59885 on the first rising edge during the
vertical serration phase. In the absence of vertical serration
pulses, a vertical sync pulse will be forced out after the
vertical sync default delay time, approximately 60µs after the
last falling edge of the vertical equalizing phase.
Horizontal Sync
The horizontal block senses the leading edges of the
composite sync signal and generates horizontal pulses of
nominal width 5.2µs. Any half line pulses present in the input
signal during vertical blanking are removed with an internal
2H line eliminator function that inhibits the retriggering of
horizontal output pulses until 70% of the line time is reached,
then the horizontal output operation is enabled again. Any
signals present on the I/P signal after the real H sync will be
ignored, thus the horizontal output will not be affected by
1
.
1
to Sync Tip Ref, thus charge is
11
1
large
1
ISL59885
,
MacroVision copy protection. When there is a loss of
incoming composite sync, the Horizontal Sync output is held
high.
C
An external C
ground. C
the Y5U general use capacitors may be too leaky and cause
faulty operation. The C
the CSET pin to reduce possible board leakage. 56nF is
recommended. Refer to the “CSET Bias Block” on page 12.
The C
a voltage on C
current for H
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is
shown in Figure16. It can be implemented very simply and
inexpensively with a series resistor of 100Ω and a capacitor
of 570pF, which gives a single pole roll-off frequency of
about 2.79MHz during NTSC or PAL. This sufficiently
attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color
burst signal, yet passes the approximately 15kHz sync
signals without appreciable attenuation. During HDTV, the
transistor turns off and a 100pF capacitor is left to filter any
noise present at the input. A chroma filter will increase the
propagation delay from the composite input to the outputs.
HD-Detect
High definition video is flagged by HD going low when the
input horizontal frequency is greater than 20kHz.
SET
VIDEO IN
SET
SET
FIGURE 16. OPTIONAL CHROMA FILTER
capacitor rectifies a 5µs pulse current and creates
SYNC
CHROMA FILTER
SET
capacitor should be a X7R grade or better as
SET
100Ω
R
100pF
C
F
capacitor connected from CSET pin 6 to
. The C
F
and V
SET
SYNC
SET
0.1µF
capacitor should be very close to
470pF
MMBT3904
C
voltage is converted to bias
timing.
F2
1
2
3
4
C
V
C
GND
SYNC
SYNC
VIN
ISL59885
10kΩ
H
C
V
OUT
SET
DD
HD
May 12, 2009
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7
6
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FN7442.7