EL4581CN Intersil, EL4581CN Datasheet
EL4581CN
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EL4581CN Summary of contents
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... Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303. EL4581 FN7172.2 PART MARKING TEMP. RANGE PACKAGE EL4581CN -40°C to +85° PDIP 4581CS -40°C to +85° SOIC 4581CSZ -40°C to +85° SOIC (Pb-free) PKG. ...
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... Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 2 EL4581 Thermal Information = +25°C) Maximum Power Dissipation See Curves Maximum Junction Temperature +150°C +0.5V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below CC http://www.intersil.com/pbfree/Pb-FreeReflow.asp = 5V +25° DESCRIPTION TEMP (° ...
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Pin Descriptions PIN NUMBER PIN NAME 1 Composite Sync Out 2 Composite Video in 3 Vertical Sync Out 4 GND 5 Burst/Back Porch Output 6 RSET (Note 8) 7 Odd/Even Output 8 VDD 5V NOTE must be a ...
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Typical Performance Curves PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 2.0 1.8 1.6 1.471W PDIP8 1.4 θ = 85°C/W JA 1.2 1.0 1.136W 0.8 0.6 SO8 0.4 θ = 110°C/W JA 0.2 0 ...
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Timing Diagrams SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE 1.5µs±230µs TIME VERTICAL BLANKING INTERVAL = 20H SYNC START OF INTERVAL FIELD ONE PRE-EQUALIZING H PULSE INTERVAL SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1 SIGNAL 1c. VERTICAL ...
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Timing Diagrams (Continued) SIGNAL 2a. COMPOSITE VIDEO INPUT SIGNAL 2b. COMPOSITE SYNC OUTPUT SIGNAL 2c. VERTICAL SYNC OUTPUT SIGNAL 2d. ODD-EVEN OUTPUT SIGNAL 2e. BURST/BACK PORCH OUTPUT SIGNAL 3a. COMPOSITE VIDEO INPUT SIGNAL 3b. VERTICAL SYNC OUTPUT 6 EL4581 SLICE ...
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INPUT DYNAMIC RANGE 0. 50% t COMPOSITE SYNC OUTPUT, PIN 1 BACK PORCH OUTPUT, PIN 5 Description of Operation A simplified block diagram is shown in Figure 13. The following description is intended to provide the user with ...
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V initiates the timing one-shots for gating the sample and hold circuits. The sample of the sync tip is delayed by 0.8µs to enable the actual sample of 2µ taken on the ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...