MAX3580ETJ+T Maxim Integrated Products, MAX3580ETJ+T Datasheet - Page 12

• Manufacturer Part Number: MAX3580ETJ+T
• Description: IC TV TUNER DIRECT-CONV 32TQFN
• Manufacturer: Maxim Integrated Products
• Type: Direct Conversion TV Tunerr

Specifications of MAX3580ETJ+T

• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Direct-Conversion TV Tuner
The MAX3580 includes thirteen write/read registers and
three read-only registers. See Table 2 for register con-
figuration and the Register Description section. The
register configuration of Table 2 shows each bit name
and the bit usage information for all registers. “U”
labeled under each bit name indicates that the bit
value is user defined to meet specific application
requirements. A “0” or “1” indicates that the bit must be
set to the defined “0” or “1” value for proper operation.
Operation is not tested or guaranteed if these bits are
programmed to other values and is only for
Table 2. Register Configuration
12
REGISTER
ADDRESS
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
0x0F
0x10
0x11
0x12
______________________________________________________________________________________
VCO_DIV1
DC_DAC7
CP_TST2
BB_BW3
TFS<7>
TFD<7>
TFR<7>
BB_BIA
VCO1A
VCO1
RDIV
POR
F15
MP
D7
N7
F7
U
U
U
U
U
U
U
U
0
0
X
0
0
0
X
0
0
X
0
VCO_DIV0
SHDN_BG
DC_DAC8
DC_DAC6
FUSE_TH
CP_TST1
BB_BW2
TFD<6>
TFR<6>
TFS<6>
VCO0A
VCO0
VASA
F14
ICP
D6
N6
LI1
F6
Detailed Description
U
U
U
U
U
U
U
U
U
0
0
0
0
0
0
X
0
Programmable Registers
SHDN_PD
DC_DAC5
CP_TST0
DC_MO1
BB_BW1
TFD<5>
TFS<5>
TFR<5>
VASE
BS2A
RFS
CPS
BS2
F13
D5
N5
LI0
F5
U
U
U
U
U
U
U
U
0
0
1
1
0
X
0
0
X
0
SHDN_REF
DC_DAC4
DC_MO0
BB_BW0
TFS<4>
TFD<4>
TFR<4>
ADLY1
TF_BS
BS1A
BS1
F12
INT
WR
D4
N4
LD
F4
U
U
U
U
U
U
U
U
U
0
X
0
1
0
0
0
X
0
8-BIT DATA
SHDN_SYN
MX_HR<3>
DC_DAC3
DC_SP1
TFD<3>
TFS<3>
TFP<3>
TFA<3>
TFR<3>
TURBO
DC_LO
ADLY0
BS0A
BS0
F19
F11
D3
N3
F3
U
U
U
U
U
U
U
U
X
U
1
1
0
1
0
0
0
MX_HR<2>
SHDN_MX
DC_DAC2
LD_MUX2
LF_DIV2
DC_SP0
TFD<2>
TFS<2>
TFP<2>
PD_TH2
TFA<2>
TFR<2>
DC_HI
ADC2
VAS
F18
F10
D2
N2
F2
U
U
U
U
U
U
U
U
U
U
U
1
0
0
0
0
factory/bench evaluation. For field use, always program
to the defined operational state. Note that all registers
must be written after and no earlier than 100µs after
device power-up.
Note 1: To correctly tune the VCO during a channel
change, first write to Register 0x05, continuing through
Register 0x06 to Register 0x12, and then write to
Register 0x00 through Register 0x04.
Note 2: Upon power-up or recovery from a supply volt-
age brownout, all registers must be written, including
the “factory use only” values. Follow up by writing the
register needed for tuning to a particular frequency per
note above or simply rewrite all registers a second time.
MX_HR<1>
SHDN_BB
DC_DAC1
LD_MUX1
LF_DIV1
PD_TH1
DC_TH1
TFA<1>
TFD<1>
TFR<1>
TFS<1>
TFP<1>
ADC1
ADL
GKT
F17
D1
N1
F9
F1
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
0
MX_HR<0>
LD_MUX0
SHDN_RF
DC_DAC0
PD_OVLD
LF_DIV0
PD+TH0
DC_TH0
TFD<0>
TFS<0>
TFP<0>
TFA<0>
TFR<0>
ADC0
ADE
F16
D0
N0
F8
F0
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
0
OPERATION
DEFINED
REGISTER SETTINGS
h38
h00
h00
h00
N/A
N/A
N/A
—
—
—
—
—
—
—
—
—
—
—
—
SETTINGS
DEFAULT
(POR)
hDB
H17
h7C
h0A
hC0
h18
h00
h00
h08
h00
h87
h40
h00
h00
h00
h00
N/A
N/A
N/A
N-Divider Integer
N-Divider Frac2
N-Divider Frac1
N-Divider Frac0
Tracking Filter
Series Caps
Tracking Filter
Parallel Cap
PLL Configuration
Test Functions
Shutdown Control
VCO Control
Baseband Control
DC Offset Control
DC Offset DAC
ROM Table
Address
ROM Table Fuse
Data
Mixer Harmonic
Rejection
ROM Table Data
Read Back
Chip Status Read
Back
Autotuner Read
Back
REGISTER
NAME