MAX3580ETJ+T Maxim Integrated Products, MAX3580ETJ+T Datasheet - Page 17

• Manufacturer Part Number: MAX3580ETJ+T
• Description: IC TV TUNER DIRECT-CONV 32TQFN
• Manufacturer: Maxim Integrated Products
• Type: Direct Conversion TV Tunerr

Specifications of MAX3580ETJ+T

• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When addressed with a write command, the MAX3580
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3580 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to. If the
slave acknowledges the address, the master can then
write one byte to the register at the specified address.
Data is written beginning with the most significant bit.
The MAX3580 again issues an ACK if the data is suc-
cessfully written to the register. The master can contin-
ue to write data to the successive internal registers with
the MAX3580 acknowledging each successful transfer,
or it can terminate transmission by issuing a STOP con-
dition. The write cycle does not terminate until the mas-
ter issues a STOP condition.
Figure 3 illustrates an example in which Registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Figure 3. Example: Write Registers 0 through 2 with 0x0E, 0xD8 and 0xE1, respectively.
Figure 4. Example: Receive data from read registers.
START
S
T
A
R
T
ADDRESS
11000000
DEVICE
WRITE DEVICE
ADDRESS
1100000
______________________________________________________________________________________
R/ W
0
R/ W
0
A
C
K
ACK
REGISTER
ADDRESS
00000000
WRITE REGISTER
ADDRESS
0x00
A
C
K
S
T
A
R
T
Write Cycle
ACK
ADDRESS
11000000
DEVICE
Direct-Conversion TV Tuner
WRITE DATA TO
REGISTER 0x00
0x0E
R/ W
1
When addressed with a read command, the MAX3580
allows the master to read back a single register or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX3580 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read. The slave acknowledges the address.
Then a START condition is issued by the master, fol-
lowed by the 7 slave address bits and a read bit (R/W =
1). The MAX3580 issues an ACK if the slave address
byte is successfully received. The MAX3580 starts send-
ing data MSB first with each SCL clock cycle. At the 9th
clock cycle, the master can issue an ACK, and continue
to read successive registers, or the master terminate the
transmission by issuing a NACK. The read cycle does
not terminate until the master issues a STOP condition.
Figure 4 illustrates an example in which Registers 0
through 2 are read back.
A
C
K
ACK
xxxxxxxx
REG 00
DATA
WRITE DATA TO
REGISTER 0x01
0xD8
A
C
K
xxxxxxxx
REG 01
DATA
ACK
WRITE DATA TO
REGISTER 0x02
A
C
K
0xE1
xxxxxxxx
REG 02
DATA
Read Cycle
ACK
N
A
C
K
STOP
O
S
T
P
17