ADV7162KS220 Analog Devices Inc, ADV7162KS220 Datasheet - Page 18

• Manufacturer Part Number: ADV7162KS220
• Description: IC DAC VIDEO COLOR 96BIT 160MQFP
• Manufacturer: Analog Devices Inc
• Type: Video DACr

Specifications of ADV7162KS220

• Rohs Status: RoHS non-compliant
• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

ADV7160/ADV7162
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 19 shows a
suggested frame buffer to ADV7160/ADV7162 interface. This is a
minimum chip solution and allows the ADV7160/ADV7162 con-
trol the overall graphics system clocking and synchronization.
PLL
The on-board PLL can be used as an alternative clock source.
This eliminates the need for an external high speed clock gen-
erator such as a crystal oscillator. With the PLL, it is possible to
generate an internal clock whose frequency is a multiple of the PLL
reference frequency (PLL
by setting CR56 of Command Register 5 to Logic “1.” The PLL
registers can be programmed to set up the frequency required.
The block diagram of the Phase Locked Loop is shown in Fig-
ure 20. The blocks consist of a phase frequency detector, a
charge pump, a loop filter, a voltage controlled oscillator and a
programmable divider.
The phase frequency detector drives the voltage controlled oscil-
lator (VCO), to a frequency that will cause the two inputs to the
phase frequency detector to be matched in frequency and phase.
The corresponding output of the VCO can be calculated as:
The Reference Divider is set by a combination of the contents of
the PLL R Register and the RSEL bit. The PLL R Register has
a resolution of 7 bits. It is programmed by setting the PLL R
Register located at Control Register address 00CH . The PLL
R Register can be set from 01H to 7FH. It should not be set to
00H. If this register contains 00H, then the PLL stops. There-
fore, the Reference Divider can be set from 3 to 129 in steps of
one, or from 130 to 258 in steps of two by setting the RSEL bit.
The RSEL bit is accessed by changing Bit PCR1 of the PLL
Control Register. The Feedback Divider is set by a combina-
tion of the contents of the PLL V Register, the VSEL bit and
the S value. The S value is set up in PCR7 and PCR6 of the
PLL Command Register. This S value allows a better resolu-
tion when setting the Feedback Divider value. The PLL V Reg-
ister has a resolution of 7 bits. It is programmed by setting the
PLL V Register located at Control Register address 00FH .The
PLL
Figure 19. ADV7160/ADV7162 Interface Using SCKIN
and SCKOUT
REF
REFERENCE
DIVIDER
VCO = PLL
VIDEO FRAME
Figure 20. PLL Block Diagram
BUFFER
F
PD
DETECTOR
F
PD
PHASE
REF
REF
). Internal PLL operation is selected
FEEDBACK
CHARGE
DIVIDER
PUMP
Feedback Divider
Reference Divider
LOADIN
SCKIN
LOADOUT
BLANK
SCKOUT
CONTROLLED
PIXEL
DATA
OSCILLATOR
VOLTAGE
ADV7160/
ADV7162
F
VCO
DIVIDER
O/P
F
OUT
–18–
PLL V Register can be set from 01H to 7FH. It should not be
set to 00H. If this register contains 00H, then the PLL stops.
Therefore the feedback divider can be set from 12 to 519 in
steps of one, or from 520 to 1038 in steps of two by setting the
VSEL bit. The VSEL bit is accessed by changing bit PCR2 of
the PLL Control Register. The P counter divides the output
from the oscillator by 1, 2, 4 or 8 as determined by PSEL1 and
PSEL0 which are set in bits PCR5 and PCR4 of the PLL Con-
trol Register. This post-scaler is useful in the generation of
lower frequencies as the VCO has been optimized for high
frequency operation.
The transfer function of the PLL can be summarized by the
block diagram shown in Figure 21.
To optimize the performance of the on-board PLL, the follow-
ing criteria should be followed:
900 kHz
300 kHz
120 MHz
For F
Any lower frequency output can be achieved by using the output
divider.
A jitter performance graph as a function of both F
illustrated in Figure 22. It can be seen that jitter decreases with
increasing F
F
ing the output divider and then pick PLL
vide to maximize FPD. When generating multiple output
frequencies from one PLL
be used to find the PLL
tween jitter performance and F
PD
. For each F
VCO
PLL
250
200
150
100
REF
> 220 MHz, V
50
0
50
VCO
F PD = 0.42MHz
F PD = 0.57MHz
F PD = 0.8MHz
F PD = 1.0MHz
F PD = 1.5MHz
F PD = 2.0MHz
F PD = 2.7MHz
F PD = 4.0MHz
F PD = 5.3MHz
F PD = 0.3MHz
Figure 21. PLL Transfer Function
(1 + VSEL)(4(V+2) + S)
F
F
F
F
F
< PLL
< F
< F
and also that jitter decreases with increasing
OUT
VCO
VCO
VCO/
VCO/
OUT
(1 + RSEL)(R+2)
/2
PD
VCO
4
8
, the user should firstly maximize F
100
Figure 22. PLL Jitter
PSEL1
0
0
1
1
REF
REF
SEL
VCO FREQUENCY – MHz
REF
value that gives the best trade off be-
PSEL0
0
1
0
1
should be programmed to logic “0.”
150
value, an iterative process should
< 40 MHz
< 10 MHz
< 260 MHz
OUT
F
VCO
PSEL1 PSEL0
accuracy.
JITTER MEASURED AT 15µs
200
REF
and reference di-
250
VCO
VCO/2
VCO/4
VCO/8
PD
and F
F
300
OUT
VCO
REV. 0
VCO
us-
is