TDA9882TS/V1,118 NXP Semiconductors, TDA9882TS/V1,118 Datasheet - Page 9

• Manufacturer Part Number: TDA9882TS/V1,118
• Description: IC IF-PLL DEMOD 24-SSOP
• Manufacturer: NXP Semiconductors
• Type: Demodulatorr

Specifications of TDA9882TS/V1,118

• Package / Case: *
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935273911118; TDA9882TS/V1-T; TDA9882TS/V1-T

Philips Semiconductors
9397 750 13507
Product data sheet
8.7 Video demodulator and amplifier
8.8 Sound carrier trap
The in-window and out-window control at the FM PLL can additionally be used to mute the
audio stage (if auto mute is selected via pins SIF1 and SIF2); see
The principle working of the digital acquisition help circuit is as follows: The PLL VCO
output is connected to a downcounter which has a predefined start value (standard
dependent). The VCO frequency clocks the downcounter for a fixed gate time. Thereafter,
the downcounter stop value is analyzed. In the event that the stop value is higher (lower)
than the expected value range, the VCO frequency will be lower (higher) than the required
lock-in window frequency range. A positive (negative) control current is injected into the
PLL loop filter which causes the VCO frequency to be increased (decreased) and a new
counting cycle starts.
The gate time as well as the control logic of the acquisition help circuit is dependent on the
precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as
well as connecting this input via a serial capacitor to an external reference frequency e.g.
the tuning system oscillator.
The AFC signal is derived from the corresponding downcounter stop value after a
counting cycle. The last four bits are latched and the digital-to-analog converted value is
given as current at pin AFC.
The video demodulator is realized by a multiplier which is designed for low distortion and
large bandwidth. The VIF signal is multiplied with the ‘in phase’ signal of the VIF PLL
VCO.
The demodulator output signal is fed into the video preamplifier via a level shift stage with
integrated low-pass filter to achieve carrier harmonics attenuation.
The output signal of the preamplifier is fed to the VIF AGC detector (see
also fed internally to the integrated sound carrier trap; see
trap output signal is converted and amplified by the following postamplifier. The video
output level at pin CVBS is 2 V (p-p).
Noise clipping is provided.
The sound carrier trap consists of a reference filter, a phase detector and the sound trap
itself.
A sound carrier reference signal is fed into the reference low-pass filter and is shifted by
nominal 90 degrees. The phase detector compares the original reference signal with the
signal shifted by the reference filter and produces a DC voltage by charging or discharging
an integrated capacitor with a current proportional to the phase difference between both
signals, respectively to the frequency error of the integrated filters. The DC voltage
controls the frequency position of the reference filter and the sound trap. Thus the
accurate frequency position for the different standards is set by the sound carrier
reference signal.
The sound trap itself is constructed of three separate traps to realize sufficient
suppression of the first and second sound carrier.
Rev. 01 — 16 November 2004
Multistandard vision and QSS FM sound IF PLL demodulator
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
Table
8.8. The differential
TDA9882
6.
Section
8.3) and
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