STV2050A STMicroelectronics, STV2050A Datasheet - Page 22

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2050A - TIMEBASES
5 TIMEBASES
5.1 LINE LOCKED PLL AND SYSTEM CLOCK
A frequency-multiplying PLL derives the internal system clock from the incoming signal at the
SYNH pin. This signal is derived from horizontal deflection.
Figure 9. Line-Locked PLL and System Clock
The PLL is designed to drive 1H, 2H, HDTV and SVGA applications. Two loop filters can be
implemented using the FILT (pin 24) and FLT2 (pin 25) pads. The selection can be forced by
the PRS bit in the D5 register.
The horizontal deflection is often turned off when switching TV set modes. Therefore the PLL
provides a base frequency when the external sync signal is missing (both H and V sync sig-
nals are missing).
22/83
SYNH
PRS
100 nF
PRS
0 = FILT selected (2H and above range operation recommended)
1 = FLT2 selected (1H range operation recommended)
15 K
10 nF
PLL
10 nF
15 K
STV2050A
1.5 nF
System
Clock