STV2050A STMicroelectronics, STV2050A Datasheet - Page 29

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1 READ OPERATION MODES
Two modes of read sequences are implemented by selecting the RWM[1:0] bits.
6.2 WRITE OPERATION MODES
Three modes of write sequences are implemented by selecting the RWM[1:0] bits.
6.3 POWER-ON SEQUENCE
At power-on, the master interface runs a special sequence to build up the convergence cor-
rection data and the STV2050A RAM is loaded with data from a user-specified EEPROM.
6.4 SECURITY FEATURE DURING DATA TRANFERS
Since access to an EEPROM register is critical with respect to system performance, all
EEPROM access commands in the E9 register, together with the corresponding addresses,
are protected by the 2-bit, error-detecting Hamming code. If the circuit detects an error, the
Master will not initiate an EEPROM access and an error bit will be set in the status register.
If any errors are detected during the transmission of data on the I²C bus, the transmission is
stopped and the corresponding STX[3] bit in the status section of the E9 register is set.
6.5 STATUS INFORMATION
Four STX[3:0] bits are available in the status section of the E9 register. These bits continu-
ously reflect the activity and the error status of the master I²C bus interface.
– STX[3] = ´TRANSMISSION ERROR´
– STX[2] = ´EEPROM ACCESS FINISHED´
– STX[1] = ´EEPROM R/W´
This bit is set to low if an error in the transmission of an EEPROM access command was
detected. It remains low until the next error-free transmission to register E9 is completed.
This bit is set to low when the master I²C-bus interface has completed bus activities. This bit
does not display the completion of an EEPROM access. This bit is set high by the master at
the start of a new bus sequence or by the slave after reading status register E9.
This bit is set to low when the master has initiated an access to the EEPROM. It remains low
until the sequence is finished or the sequence is terminated by an access error.
RWM[1:0]
RWM[1:0]
11 (bin): Read all convergence data and an ADS
10 (bin): Read an ADS only
01 (bin): Write all convergence data and one of the three ADSs
00 (bin): Write only one of the ADSs
10 (bin): Write only the “static” (position offset) values
STV2050A - MASTER I²C BUS INTERFACE
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