74ABT544PW,112 NXP Semiconductors, 74ABT544PW,112 Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
74ABT544PW,112
Manufacturer Part Number
74ABT544PW,112
Description
IC TRANSCVR 3ST 8BIT INV 24TSSOP
Manufacturer
NXP Semiconductors
Series
74ABTr
Datasheet
1.74ABT544PW112.pdf
(16 pages)
Specifications of 74ABT544PW,112
Logic Type
Transceiver, Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-2487-5
935178850112
935178850112
NXP Semiconductors
6. Functional description
Table 3.
[1]
74ABT544
Product data sheet
Input
OEXX
H
X
L
L
L
L
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
Function selection
6.1 Function table
6.2 Description
EXX
X
H
↑
L
L
L
The 74ABT544 contains two sets of eight D-type latches, with separate control pins for
each set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output enable (OEAB) input are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
[1]
X
L
H
LEXX
X
L
↑
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 20 May 2010
An or Bn
X
X
h
l
h
l
H
L
X
Octal latched transceiver with dual enable; 3-state
Output
Bn or An
Z
Z
Z
Z
L
H
L
H
NC
74ABT544
Status
disabled
disabled + latch
latch + display
transparent
hold
© NXP B.V. 2010. All rights reserved.
4 of 16