IR3895MTRPBF International Rectifier, IR3895MTRPBF Datasheet - Page 23
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IR3895MTRPBF
Manufacturer Part Number
IR3895MTRPBF
Description
16A Highly Integrated Single-Input Voltage, Synchronous Buck Regulator in a PQFN package.
Manufacturer
International Rectifier
Datasheet
1.IR3895MTR1PBF.pdf
(42 pages)
Specifications of IR3895MTRPBF
Part Status
Active and Preferred
Package
PQFN / 5 x 6
Circuit
Single Output
Iout (a)
16
Switch Freq (khz)
0 - 1500
Input Range (v)
1.0 - 16
Output Range (v)
0.5 - 12
Pbf
PbF Option Available
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IR3895MTRPBF
Manufacturer:
IR
Quantity:
20 000
VREF
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to an
external bypass capacitor and it is left floating. A minimum
100pF ceramic capacitor is required from stability point of
view. To keep stand by current to minimum, Vref is not
allowed come up until EN starts going high. In tracking
mode this pin should be pulled to GND. For margining
applications, an external voltage source is connected to
Vref pin and overrides the internal reference voltage. The
external voltage source should have a low internal
resistance (<100Ω) and be able to source and sink more
than 25µA.
POWER GOOD OUTPUT (TRACKING,
SEQUENCING, VREF MARGINING)
IR3895 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input to
the window comparator with upper and lower threshold of
0.6V and 0.45V respectively. PGood signal is high
whenever Vsns voltage is within the PGood comparator
window thresholds. The PGood pin is open drain and it
needs to be externally pulled high. High state indicates that
output is in regulation.
The threshold is set differently at different operating
modes and the results of the comparison sets the PGood
signal. Figures 15, 16, and 17 show the timing diagram of
the PGood signal at different operating modes. Vsns signal
is also used by OVP comparator for detecting output over
voltage condition.
Figure 15: Non‐sequence, Non‐tracking Startup
23
and Vref Margin (Vp pin floating)
FEBRUARY 01, 2012 | DATA SHEET| Rev 3.0
Single‐Input Voltage, Synchronous Buck Regulator
- 23 -P
16A Highly Integrated SupIRBuck
OVER‐VOLTAGE PROTECTION (OVP)
Over‐voltage protection in IR3895 is achieved by
comparing sense pin voltage Vsns to a pre‐set threshold.
In non‐tracking mode, OVP threshold can be set at
1.2*Vref; in tracking mode, it can be at 1.2*Vp. When Vsns
exceeds the over voltage threshold, an over voltage trip
signal asserts after 2us (typical.) delay. Then the high side
drive signal HDrv is turned off immediately, PGood flags
low. The low side drive signal is kept on until the Vsns
voltage drops below the threshold. After that, HDrv is
latched off until a reset performed by cycling either Vcc or
Enable.
Vsns voltage is set by the voltage divider connected to the
output and it can be programmed externally. Figure 18
shows the timing diagram for OVP in non‐tracking mode.
PGood
Vsns
0
0
0
Vp
0.4V
1.28ms
Figure 17: Vp Sequence and Vref Margin
Figure 16: Vp Tracking (Vref =0V)
0.9*Vp
1.2*Vp
IR3895
PD‐97746
0.3V