FDMF6708N Fairchild Semiconductor, FDMF6708N Datasheet - Page 14

• Manufacturer Part Number: FDMF6708N
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6708N • Rev. 1.0.2
Zero Cross Detection Mode (ZCD_EN#)
The Zero Current Detection Mode allows for higher
converter
conditions. When ZCD_EN# is pulled LOW; the low-side
MOSFET gate signal pulls LOW when internal circuitry
detects positive LS MOSFET drain current, preventing
discharge of the output capacitors as the filter inductor
current attempts reverse current flow – known as “Diode
Emulation” Mode.
When the ZCD_EN# pin is pulled HIGH, the synchronous
buck converter works in Synchronous Mode. This mode
allows for gating of the low-side MOSFET.
Table 2.
Note:
4.
ZCD_EN#
GL = 0, when I
current is positive and flowing out of the DrMOS VSWH node).
VSWH
GH to
PWM
VSWH
GL
DISB#
V
IH_PWM
0
1
1
1
1
1
efficiency
ZCD_EN# Logic
t
PD_PHGLL
t
D_DEADON
L
< 0 (Inductor current is negative and flowing in to the DrMOS VSWH node). GL = 1 when I
1.7V
90%
t
PD_PLGHL
when
t
D_DEADOFF
V
90%
3-State
IL_PWM
PWM
1.7V
operating
X
0
1
0
1
10%
Figure 30.
I
L
> 0
in
GL transitions
detected and
I
V
L
low.
< 0
light-load
IL_ZCD_EN
ZCD_EN#
ZCD_EN# Timing Diagram
X
X
0
0
1
1
14
going high to LS V
Delay from ZCD_EN#
V
When the ZCD_EN# pin is pulled LOW, the low-side
MOSFET is gated off automatically during positive LS
MOSFET drain current. If the ZCD_EN# pin is pulled
LOW by the PWM controller to support light-load Power-
Saving Mode, FDMF6708N can actively turn off the low-
side MOSFET when it detects the zero crossing of the
inductor current. The low-side MOSFET turns on when
inductor current is positive (LS MOSFET drain current is
negative) and turns off when inductor current is negative
(LS MOSFET drain current is positive). Zero-crossing
detection of the inductor current and low-side MOSFET
on and off are automatically performed on a cycle-by-
cycle basis. Normally this pin is active LOW. See Figure
30 for timing delays.
IH_ZCD_EN
DCM (I
t
PD_ZHGLH
GS
L
= 0)
high
10%
t
PD_ZLGLL
GH
going low to LS V
Delay from ZCD_EN#
0
0
0
1
0
1
V
IL_ZCD_EN
90%
V
GS
DCM
IH_PWM
low
t
PD_PHGLL
0 (I
L
L
<0),1 (I
> 0 (Inductor
1 0%
GL
0
0
0
1
0
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L
> 0)
V
OUT
(4)