FDMF6706B Fairchild Semiconductor, FDMF6706B Datasheet - Page 13

• Manufacturer Part Number: FDMF6706B
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6706B • Rev. 1.0.1
Adaptive Gate Drive Circuit
The driver IC design ensures minimum MOSFET dead
time, while eliminating potential shoot-through (cross-
conduction) currents. It senses the state of the MOSFETs
and adjusts the gate drive adaptively to prevent
simultaneous conduction. Figure 25 provides the relevant
timing waveforms. To prevent overlap during the LOW-to-
HIGH switching transition (Q2 off to Q1 on), the adaptive
circuitry monitors the voltage at the GL pin. When the
PWM signal goes HIGH, Q2 turns off after a propagation
delay (t
~1V, Q1 turns on after adaptive delay, t
VSWH
VSWH
PWM
GH
GL
to
V
IH_PWM
Notes:
t
t
PWM
t
t
t
SMOD#
t
t
PD_xxx
D_xxx
PD_PHGLL
PD_PLGHL
PD_PHGHH
PD_SLGLL
PD_SHGLH
t
CCM
PD_PHGLL
PD_PHGLL
= delay from IC generated signal to IC generated signal.
= propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
t
= SMOD# fall to LS V
= PWM rise to LS V
= PWM fall to HS V
= SMOD# rise to LS V
D_DEADON
= PWM rise to HS V
1.0V
90%
). Once the GL pin is discharged below
t
PD_PLGHL
V
t
IL_PWM
GS
GS
D_DEADOFF
GS
GS
fall, V
fall, V
GS
rise, V
fall, V
t
rise, V
2.2V
R_GL
IH_PWM
IL_PWM
IL_SMOD
IH_PWM
10%
IH_SMOD
t
less than
D_HOLD - OFF
to 90% HS V
to 90% LS V
to 90% LS V
to 10% HS V
to 10% LS V
Figure 25.
t
D_HOLD - OFF
D_DEADON
GS
GS
GS
GS
Enter
GS
3 -State
(SMOD# held LOW)
t
F_GL
DCM
Example (t
.
V
PWM and 3-StateTiming Diagram
IH_PWM
Exit
D_DEADON
3-State
t
t
R_GH
PD_TSGHH
– LS V
13
To prevent overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the VSWH pin. When the PWM signal goes
LOW, Q1 turns off after a propagation delay (t
Once the VSWH pin falls below ~2.2V, Q2 turns on after
adaptive delay t
monitored. When V
secondary adaptive delay is initiated that results in Q2
being driven on after t
state. This function ensures C
switching cycle in the event that the VSWH voltage does
not fall below the 2.2V adaptive threshold. Secondary
delay, t
GS
t
(GL) LOW to HS V
D_HOLD -OFF
V
Exiting 3-state
t
t
Dead Times
t
t
PD_TSGHH
PD_TSGLH
D_DEADON
D_DEADOFF
TRI_HI
3 -State
Enter
t
Example (t
F_GH
D_TIMEOUT
= PWM 3-state to LOW to LS V
= PWM 3-state to HIGH to HS V
= LS V
= VSWH fall to LS V
DCM
GS
GS
PD_PHGLL
fall to HS V
(GH) HIGH)
V
IH_PWM
is longer than t
– PWM going HIGH to LS V
t
PD_TSGHH
D_DEADOFF
Exit
3 State
GS(Q1)
GS
GS
rise, LS-comp trip value (~1.0V GL) to 10% HS V
rise, SW-comp trip value (~2.2V VSWH) to 10% LS V
D_TIMEOUT
is discharged below ~1.2V, a
GS
t
less than
D_HOLD - OFF
GS
rise, V
. Additionally, V
rise, V
D_DEADOFF
BOOT
IL_PWM
IH_PWM
, regardless of VSWH
GS
(GL) going LOW)
to 10% LS V
t
to 10% HS V
D_HOLD -OFF
is recharged each
3 -State
Enter
.
GS
www.fairchildsemi.com
GS
t
PD_TSGLH
3- State
Exit
PD_PLGHL
GS(Q1)
V
V
V
V
IH PWM
TRI_LO
TRI_HI
IL_PWM
V
V
GS
90%
10%
90%
10%
OUT
IN
GS
is
).