FAN5355 Fairchild Semiconductor, FAN5355 Datasheet - Page 23

• Manufacturer Part Number: FAN5355
• Description: The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.0
Bit Definitions
The following table defines the operation of each register bit. Superscript characters define the default state for each option.
Superscripts
Bit Name
VSEL0
VSEL1
CONTROL1
CONTROL2
5:0
5:0
7:6
3:2 MODE_CTRL
4:3
2:0
7
6
7
6
5
4
1
0
7
6
5
DISCHARGE
PLL_MULT
EN_DCDC
EN_DCDC
EN_SYNC
(read only)
DEFSLEW
OUTPUT_
Reserved
Reserved
Reserved
HW_nSW
DAC[5:0]
DAC[5:0]
PWROK
MODE1
MODE0
GO
0,2,3,6,8
Value Description
signify the default values for options 00, 02, 03, 06, and 08 respectively.
Table
Table
111
10
000
001
010
011
100
101
110
00
00
10
10
01
10
11
01
10
11
1
1
0
1
0
0
0
0
0
1
0
1
1
0
1
1
1
1
0
1
A
A
A
A
A
A
A
A
A
A
A
A
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either
register establishes the EN_DCDC value.
Device enabled when EN pin is HIGH, disabled when EN is LOW.
6-bit DAC value to set V
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL0. A write to bit 7 in either
register establishes the EN_DCDC value.
Device enabled when EN pin is HIGH, disabled when EN is LOW.
6-bit DAC value to set V
Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be used to distinguish
between vendors via I
Disables external signal on SYNC from affecting the regulator.
When a valid frequency is detected on SYNC, the regulator synchronizes to it and PFM is disabled, except
when MODE = 00, VSEL pin = LOW, and HW_nSW = 1.
V
V
Operation follows MODE0, MODE1.
PFM with automatic transitions to PWM, regardless of VSEL.
PFM disabled (forced PWM), regardless of VSEL.
Unused.
PFM disabled (forced PWM) when regulator output is controlled by VSEL1.
PFM with automatic transitions to PWM when regulator output is controlled by VSEL1.
PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the operation of
the regulator.
This bit has no effect when HW_nSW = 1.
Starts a V
transition to start, even if its value might have already been 1 from the last V
When the regulator is disabled, V
When the regulator is disabled, V
V
V
f
f
f
f
V
V
V
V
V
V
V
Positive V
SW
SW
SW
SW
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= f
= 2 X f
= 3 X f
= 4 X f
Register Address: 00
Register Address: 01
Register Address: 02
Register Address: 03
is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit.
is programmed by the VSEL pin. V
is not in regulation or is in current limit.
is in regulation.
slews at 0.15mV/  s during positive V
slews at 0.30mV/  s during positive V
slews at 0.60mV/  s during positive V
slews at 1.20mV/  s during positive V
slews at 2.40mV/  s during positive V
slews at 4.80mV/  s during positive V
slews at 9.60mV/  s during positive V
SYNC
OUT
SYNC
SYNC
SYNC
OUT
when synchronization is enabled.
transition if HW_nSW = 0. This bit must be written by the external master to 1 for the next V
transitions use single-step mode (see Figure 39) .
when synchronization is enabled.
when synchronization is enabled.
when synchronization is enabled.
2
C.
OUT
OUT
.
.
OUT
OUT
is not discharged.
discharges through an internal pull down.
23
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW.
transitions.
transitions.
transitions.
transitions.
transitions.
transitions.
transitions.
A
signifies the default for all options.
OUT
transition.
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OUT