FAN5355 Fairchild Semiconductor, FAN5355 Datasheet - Page 3

• Manufacturer Part Number: FAN5355
• Description: The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.0
Pin Configuration
Pin Definitions
Note:
5.
WLCSP
A1, B1
C1
C2
C3
D1
D2
D3
A2
A3
B2
B3
All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I
Pin #
Top View
8, PAD
MLP
N/A
10
Figure 2. WLCSP-12, 2.23x1.46mm
9
1
2
7
3
6
5
4
Name
PGND
AGND
SYNC
VOUT
VSEL
PVIN
AVIN
SDA
SCL
SW
EN
(5)
Description
Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB.
The connection from this pin to the bottom of C
Switching Node. Connect to output inductor.
Power Input Voltage. Connect to input power source. The connection from this pin to C
should be as short as possible.
Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency
on this pin. In PWM mode, when this pin is statically LOW or statically HIGH, or when its
frequency is outside of the specified capture range, the regulator’s frequency is controlled by
its internal 3MHz clock.
Analog Input Voltage. Connect to input power source as close as possible to the input
bypass capacitor.
Analog GND. This is the signal ground reference for the IC. All voltage levels are measured
with respect to this pin.
Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is
minimized. This pin should not be left floating.
SDA. I
Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the
control circuit and does not carry DC current.
Voltage Select. When HIGH, V
behavior can be overridden through I
SCL. I
2
2
C interface serial clock.
C interface serial data.
Bottom View
3
OUT
is set by VSEL1. When LOW, V
2
C register settings. This pin should not be left floating.
2
C control is unused, tie SDA and SCL to AVIN.
IN
should be as short as possible.
Figure 3. MLP10, 3x3mm
Top View
OUT
is set by VSEL0. This
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IN