TLE 7273-2E V50 Infineon Technologies, TLE 7273-2E V50 Datasheet - Page 9

• Manufacturer Part Number: TLE 7273-2E V50
• Manufacturer: Infineon Technologies

Specifications of TLE 7273-2E V50

• Packages: PG-SSOP-14
• Regulator Type: single output
• Output Voltage: 5V
• Accuracy: 2.0 %
• Max. Output Current: 180mA
• Dropout Voltage: 250mV

is in the very first turn after power up a long open window with tmax = 4 *
corresponds to the standard timing setting as described in the specification.
When a valid trigger signal is detected during the open window a closed window is initialized immediately. A trigger
signal within the closed window is interpreted as a pretrigger failure and results in a reset. After the closed window
the open window with the duration
has occurred, at maximum
A HIGH to LOW transition of the watchdog trigger signal at pin WDI is considered as a valid trigger pulse.
See
(sample period
A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs
during the closed window. The triggering is correct also, if the first three samples (two HIGH one LOW) of the
trigger pulse at pin WDI are inside the closed window and only the fourth sample (the second LOW sample) is
taken in the open window.
After turning OFF the Watchdog by output current reduction, RO remains high. (see also the signal diagram in
Figure
the Ignore Window and goes then into the “1st. long open window”. This 1st long OW is maximum 4 *
allows the re-synchronisation between the micro controller and the WWD timing. The 1st. long OW is closed by
the first valid trigger on WDI from the mirco controller. This trigger ensures the synchronisation. As soon as this
trigger is done, the micro controller timing must be stable and correspondent to
Figure 5
Data Sheet
Figure
6). After turning ON the WWD again by exceeding the current threshold, the logic cycle starts again with
7: To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two LOW samples
Window Watchdog State Diagram, Watchdog and Reset Modes
t
sam
typ. 0.5 ms) are decoded as a valid trigger .
Window
Trigger
Closed
t
Reset
OW
Trigger During
Closed Window
is 32 ms (typ. value with fast timing).
t
WM1
WM2
Window Watchdog Mode
Reset Mode
OW
is started again. The open window lasts at minimum until the trigger process
No Trigger
No Trigger During
Open Window
Always
Trigger
Fast
Fast
9
L
L
Window
Window
Ignore
Open
Always
Block Description and Electrical Characteristics
Slow
Slow
H
L
Slow
Fast
H
L
AEA03527_1.VSD
IQ < 0.5mA
IQ > 5mA
Slow
Always
Off
H
H
t
OW
. In the following turns, the timing
Watchdog
t
WD
OFF
.
Rev. 1.2, 2009-04-28
TLE7273-2
t
OW
long and