TLE 8201R Infineon Technologies, TLE 8201R Datasheet - Page 6

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TLE 8201R

Manufacturer Part Number
TLE 8201R
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of TLE 8201R

Packages
PG-DSO-36
Ipeak
8.0 A peak for OUT 1.2 ; 6.25 A peak for OUT 7
Inhibit
Y
Iq (typ)
0.2 µA2.5 µA
Mounting
SMT
Technology
BCD
Pin
13
14
16, 17
20, 21
22
24
25
27
28
29
31, 32
34
35
Data Sheet Rev. 2.0
Symbol
DI
GO
OUT1
OUT2
OUT3
OUT11
OUT10
CP
OUT9
OUT8
OUT7
OUT4
n.c.
Function
Serial Data Input; Receives serial data from the master when
the chip is selected by CSN=LOW. Data transmission is
synchronized by CLK. Data are accepted on the falling edge of
CLK. The LSB is transferred first. The DI-pin has an internal pull-
down current source.
Gate Out; Charge pump output to drive the gate of external n-
channel MOS-FET for reverse polarity protection
Power-Output of half-bridge 1; DMOS half-bridge.
Power-Output of half-bridge 2; DMOS half-bridge.
Power-Output of half-bridge 3; DMOS half-bridge
Power Output of high-side switch 11; DMOS high-side switch
Power Output of high-side switch 10; DMOS high-side switch
Charge Pump; pin for optional external charge-pump reservoir
capacitor. 3.3 nF to Vs is recommended
Power-Output of high-side switch 9; DMOS high-side switch
Power-Output of high-side switch 8; DMOS high-side switch
Power Output of high-side switch 7; DMOS high-side switch
Power-Output of half-bridge 4; DMOS half-bridge
Not connected
6
Pin Configuration
TLE 8201R
2006-06-07

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