TLE 8203E Infineon Technologies, TLE 8203E Datasheet - Page 15

• Manufacturer Part Number: TLE 8203E
• Manufacturer: Infineon Technologies

Specifications of TLE 8203E

• Packages: PG-DSO-36
• Ipeak: 6.25 A for OUT 7
• Inhibit: Y
• Iq (typ): 0.2 µA2.5 µA
• Mounting: SMT
• Technology: BCD

Table 3
Bit
2
1
0
Note: x-bits are set to low
Table 4
Status Bit
LSxOvL
HSxOvL
LSxOpL
HSxOpL
PSF
TSD
TW
EF_xy
N.C.
7.4
The SPI is using a standard shift-register concept with daisy-chain capability. Any data transmitted to the SPI will
be available to the internal logic part at the end of the SPI transmission (CSN L -> H). To read a specific register,
the address of the register is sent by the master to the SPI in a first SPI frame. The data that corresponds to this
address is transmitted by the SPI DO during the following (second) SPI frame to the master. The default address
for Status Register transmission after Power-ON Reset is 00.
The Status-Register-Reset command-bit is executed after the next SPI transmission. The three bits RA_0, RA_1
and SRR act as command to read and reset (or not reset) the addressed Status-Register. This is also explained
in
The TSD status bit is not part of the addressable data but of the address independent data. When any of the status
registers is reset, the TSD bit is reset, too.
Final Data Sheet
Figure
StatReg 00
Lock and Mirror Heat
Overload
EF_11
EF_10
EF_01
5.
Output (Status) Data Register (cont’d)
Status Bit Definitions
Status Register Address Selection and Reset
Definition
Low-Side switch Over Load. Set to HIGH if low-side switch no. x is shut down due to overcurrent
or overtemperature or crosscurrent.
High-Side switch Over Load. Set to HIGH if high-side switch no. x is shut down due to
overcurrent or overtemperature or crosscurrent.
Low-Side switch open load. Set to HIGH if open load (undercurrent) is detected in low-side
switch x.
High-Side switch Open Load. Set to HIGH if open load is detected in high-side switch x.
Power Supply Fail. Set to HIGH if the Voltage at the
threshold or above the
All powerstages are shut down due to overtemperature.
One or more powerstages have reached the warning temperature.
Error Flag for StatReg xy. Set to HIGH if any bit is set to HIGH StatReg xy.
Not connected. These bits may be used for test-mode purposes. They are set to fixed LOW in
normal operation.
StatReg 01
Lock and Mirror Heat
Open Load
EF_11
EF_10
EF_00
V
S
overvoltage threshold.
15
StatReg 10
Mirror and Lamp-driver
Overload
EF_11
EF_01
EF_00
V
S
pin is below the
StatReg 11
Mirror and Lamp-driver
Open Load
EF_10
EF_01
EF_00
V
S
Rev. 1.0, 2009-02-04
undervoltage
TLE 8203E
SPI