TLE8108EM Infineon Technologies, TLE8108EM Datasheet - Page 23

• Manufacturer Part Number: TLE8108EM
• Manufacturer: Infineon Technologies

Specifications of TLE8108EM

• Packages: PG-SSOP-24
• Thermal Class: Exposed Pad
• Id Nom: 8 x 0.5 A
• Pin Count: 24.0 Pins
• Channels: 8.0
• Comment: 8 channel realy and LED driver

8.2
The SPI of TLE8108EM provides daisy chain capability. In this configuration several devices are activated by the
same CS signal (MCS). The SI line of one device is connected with the SO line of another device (see
to build a chain. The terminations of the chain are connected with the output and input of the master device, MO
and MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of
each device in the chain.
Figure 12
In the SPI block of each device, there is a shift register where one bit from SI line is shifted at each SCLK. The bit
shifted out can be seen at SO. After 16 SCLK cycles, the data transfer for one TLE8108EM has been finished. In
single chip configuration, the CS line must go high to make the device accepting the transferred data. In daisy
chain configuration the data shifted out at device #1 is shifted in at device #2. When using multiple devices in daisy
chain, the number of transferred bits must correspond to the number of the register bits of all chained devices.
Figure 13
a successful transmission, there must be (2*16 + 1*8)-bit shifted through the devices. After that, the MCS line can
go high.
Figure 13
Data Sheet
MCLK
MCS
MO
shows an example with 3 SPI devices, where #1 and #3 are 16-bit SPI and #2 has a 8-bit SPI. To get
MI
Daisy Chain Capability
Daisy Chain Configuration
Data Transfer in Daisy Chain Configuration
MCLK
MCS
MO
MI
SI
SCLK
CS
Slave 1
SO device 3
SI device 3
SPI
SO
SO device 2
23
SI device 2
SI
SCLK
CS
Slave 2
SPI
Smart 8-Channel Low Side Switch
SO
SI device 1
SO device 1
Serial Peripheral Interface (SPI)
SPI Daisy Chain data Transfer.vsd
SI
SCLK
CS
Rev. 1.0, 2011-03-23
Slave 3
SPI Daisy Chain.vsd
TLE 8108 EM
SPI
SO
t
Figure
12),