SAF-C161K-LM Infineon Technologies, SAF-C161K-LM Datasheet - Page 45

• Manufacturer Part Number: SAF-C161K-LM
• Manufacturer: Infineon Technologies

Specifications of SAF-C161K-LM

• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 1.0 KByte
• Program Memory: 0.0 KByte

Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 12
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
Data Sheet
Memory Cycle Variables
t
Symbol
t
t
t
t
t
t
t
t
A
5
6
7
8
9
10
11
12
+
t
CC 10 +
CC 4 +
CC 10 +
CC 10 +
CC -10 +
CC –
CC –
CC 30 +
C
+
Symbol
t
t
t
A
C
F
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
A
t
t
t
t
41
A
A
A
t
C
A
Values
TCL
2TCL
2TCL
max.
–
–
–
–
–
6
26
–
<ALECTL>
(15 - <MCTC>)
(1 - <MTTC>)
1 / 2TCL = 1 to 25 MHz
min.
TCL - 10
+
TCL - 16
+
TCL - 10
+
TCL - 10
+
-10 +
–
–
2TCL - 10
+
Variable CPU Clock
t
t
t
t
t
A
A
A
A
C
t
A
max.
–
–
–
–
–
6
TCL + 6
–
V2.0, 2001-01
C161O
C161K
Unit
ns
ns
ns
ns
ns
ns
ns
ns