AT91SAM9260-QU ATMEL Corporation, AT91SAM9260-QU Datasheet
AT91SAM9260-QU
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AT91SAM9260-QU Summary of contents
Page 1
... Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected ® ® Thumb Processor ® ® Technology for Java Acceleration AT91 ARM Thumb ® Microcontrollers AT91SAM9260 6221G–ATARM–31-Jan-08 ...
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... VDDBU, VDDCORE and VDDPLL – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 208-lead PQFP Green and a 217-ball LFBGA Green Package AT91SAM9260 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ...
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... The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ler. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface ...
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... Figure 2-1. AT91SAM9260 Block Diagram AT91SAM9260 4 Filter 6221G–ATARM–31-Jan-08 ...
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... Output Shutdown, Wakeup Logic Output Input ICE and JTAG Input Input Input Output Input Input Output Reset/Test I/O AT91SAM9260 Active Level Comments 1.65V to 1.95V or 3.0V to3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 1.95V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V Accepts between 0V and VDDBU. Driven at 0V only. Do not tie over VDDBU. ...
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... CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash Chip Select Lines AT91SAM9260 6 Type Input Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA - PIOB - PIOC ...
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... Output SDRAM Controller Output Output Output Output Output Output Output Multimedia Card Interface MCI Output I/O I/O I/O I/O I/O I/O Input Output Input Output Input Input Input Synchronous Serial Controller - SSC Output Input I/O I/O I/O I/O AT91SAM9260 Active Level Comments Low Low Low Low Low High Low Low Low 7 ...
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... Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier Sense and Data Valid ECOL Collision Detect EMDC Management Data Clock EMDIO Management Data Input/Output EF100 Force 100Mbit/sec. AT91SAM9260 8 Type Timer/Counter - TCx Input I/O I/O Serial Peripheral Interface - SPIx_ I/O I/O I/O I/O Output Two-Wire Interface I/O ...
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... Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ADTRG ADC Trigger 6221G–ATARM–31-Jan-08 Type Image Sensor Interface Input Output Input Input Input Analog to Digital Converter Analog Analog Input AT91SAM9260 Active Level Comments Digital pulled-up inputs at reset 9 ...
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... PQFP Green package (0.5mm pitch) • 217-ball LFBGA Green package (0.8 mm ball pitch) 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character- istics” of the product datasheet. Figure 4-1. AT91SAM9260 10 shows the orientation of the 208-pin PQFP package. ...
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... A9 140 A8 141 VDDIOM 142 GND 143 A7 144 A6 145 A5 146 A4 147 A3 148 A2 149 NWR2/NBS2/A1 150 NBS0/A0 151 SDA10 152 AT91SAM9260 Signal Name Pin Signal Name RAS 157 ADVREF D0 158 PC0 D1 159 PC1 D2 160 VDDANA D3 161 PB10 D4 162 PB11 D5 163 PB20 D6 164 ...
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... SHDN 101 50 HDMA 102 51 HDPA 103 52 VDDIOP0 104 4.3 217-ball LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character- istics” of the product datasheet. Figure 4-2. AT91SAM9260 12 Signal Name Pin CFIOW/NBS3/NWR3 153 CFIOR/NBS1/NWR1 154 SDCS/NCS1 155 CAS 156 shows the orientation of the 217-ball LFBGA package. ...
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... H4 D11 P2 H8 GND P3 H9 GND P4 H10 GND P5 H14 VDDCORE P6 H15 TCK P7 H16 NTRST P8 H17 PB18 P9 J1 PC19 P10 AT91SAM9260 Signal Name Pin Signal Name TDO P17 PB5 PB19 R1 NC TDI R2 GNDANA PB16 R3 PC29 PC24 R4 VDDANA PC20 R5 PB12 D15 R6 PB23 PC21 R7 GND ...
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... GNDBU, GNDPLL and GNDANA. 5.2 Power Consumption The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises the temperature increases to 85°C. On VDDBU, the current does not exceed 10 µA in worst case conditions. ...
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... NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Charac- teristics” in the product datasheet. The NRST signal is inserted in the Boundary Scan. ...
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... The SHDN pin is an output only, which is driven by the Shutdown Controller. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 6.7 Slow Clock Selection The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator. Table 6-1 Table 6-1. ...
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... Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset 6221G–ATARM–31-Jan-08 each quarter of the page system flexibility 32-bit data interface (Words) or fixed default master internal boot, one for external boot, one after remap AT91SAM9260 17 ...
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... Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... USART1 Receive Channel – USART0 Receive Channel – ADC Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC Receive Channel 6221G–ATARM–31-Jan-08 AT91SAM9260 Masters to Slaves Access Internal ROM X UHP User Interface X External Bus Interface X Internal Peripherals ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins AT91SAM9260 20 6221G–ATARM–31-Jan-08 ...
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... Memories Figure 8-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3/ ...
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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: AT91SAM9260 22 Table 8-1, “Internal Memory Mapping,” on page 22 Figure 8-1 on page summarizes the Internal Memory Mapping for each Master, depending on the Remap ...
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... The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface ...
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... Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported AT91SAM9260 24 6221G–ATARM–31-Jan-08 ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6221G–ATARM–31-Jan-08 detected erroneous pages AT91SAM9260 25 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 9-1 on page 27 Figure 8-1 on page 21 peripherals. AT91SAM9260 26 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6221G–ATARM–31-Jan-08 ...
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... Block Diagram Figure 9-1. AT91SAM9260 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSC_SEL SLOW XIN32 CLOCK OSC XOUT32 XIN MAIN OSC XOUT PLLRCA PLLA ...
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... Embeds 2 PLLs – PLLA outputs 80 to 240 MHz clock – PLLB outputs 70 to 130 MHz clock – Both integrate an input divider to increase output accuracy – PLLB embeds its own filter AT91SAM9260 28 reset, user reset or watchdog reset 6221G–ATARM–31-Jan-08 ...
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... On Chip RC OSC XIN32 Slow Clock Oscillator XOUT32 XIN Main Oscillator XOUT PLL and PLLRCA Divider A PLL and Divider B Status Control Power Management Controller processor stopped waiting for an interrupt AT91SAM9260 Slow Clock SLCK Main Clock MAINCK PLLA Clock PLLACK PLLB Clock PLLBCK 29 ...
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... Figure 9-3. AT91SAM9260 Power Management Controller Block Diagram Master Clock Controller SLCK MAINCK PLLACK PLLBCK 9.6 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux 9.7 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.12 Chip Identification • Chip ID: 0x019803A2 • JTAG ID: 0x05B1303F • ARM926 TAP ID: 0x0792603F 6221G–ATARM–31-Jan-08 enabled processor Generator the ARM Processor’s ICE Interface AT91SAM9260 ® USART 31 ...
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... AT91SAM9260 32 defines the Peripheral Identifiers of the AT91SAM9260. A peripheral identifier is AT91SAM9260 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC - - TC0 TC1 ...
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... IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions ...
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... PA26 TIOA0 ERX3 PA27 TIOA1 ERXCK PA28 TIOA2 ECRS PA29 SCK1 ECOL (1) PA30 SCK2 RXD4 (1) PA31 SCK0 TXD4 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 34 Application Usage Comments Reset State Power Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ...
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... TIOB5 I/O ISI_D0 I/O ISI_D1 I/O ISI_D2 I/O ISI_D3 I/O ISI_D4 I/O ISI_D5 I/O ISI_D6 I/O ISI_D7 I/O ISI_PCK I/O ISI_VSYNC I/O ISI_HSYNC I/O ISI_MCK I/O AT91SAM9260 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 ...
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... PC23 D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 36 Peripheral B Comments Reset State SCK3 AD0 I/O PCK0 AD1 I/O PCK1 AD2 I/O SPI1_NPCS3 AD3 I/O SPI1_NPCS2 A23 SPI1_NPCS1 ...
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... RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation 6221G–ATARM–31-Jan-08 peripherals Sensors and data per chip select AT91SAM9260 37 ...
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... Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features ...
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... Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory 6221G–ATARM–31-Jan-08 AT91SAM9260 39 ...
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... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals AT91SAM9260 40 6221G–ATARM–31-Jan-08 ...
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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA • separate instruction and data TCM interfaces 6221G–ATARM–31-Jan-08 ™ integer core ™ AHB bus interfaces AT91SAM9260 ™ family of general-purpose microproces- 41 ...
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... Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 11.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC AT91SAM9260 42 ARM926EJ-S Coprocessor Interface Droute ...
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... User mode is the usual ARM program execution state used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 6221G–ATARM–31-Jan-08 AT91SAM9260 43 ...
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... Table 11-1 Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR AT91SAM9260 44 shows all the registers in all modes. ™ ARM9TDMI Modes and Registers Layout Supervisor Mode Abort Mode ...
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... The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 6221G–ATARM–31-Jan-08 AT91SAM9260 45 ...
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... Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) AT91SAM9260 Reserved Jazelle state bit ...
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... ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 6221G–ATARM–31-Jan-08 into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. AT91SAM9260 47 ...
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... MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP AT91SAM9260 48 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
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... Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR AT91SAM9260 Mnemonic Operation MRRC Move double from coprocessor Alternative move of ARM reg to MCR2 coprocessor MCRR Move double to coprocessor Alternative Coprocessor Data ...
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... ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Register AT91SAM9260 50 Thumb Instruction Mnemonic List (Continued) Operation Logical Shift Left Arithmetic Shift Right Multiply Branch ...
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... Register locations 0, 5 and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. AT91SAM9260 Read/Write Read/write Read/write ...
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... L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. AT91SAM9260 52 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...
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... Mapping Details Mapping Size Access Permission By 1M byte Section 64K bytes 4 separated subpages 4K bytes 4 separated subpages 1K byte Tiny Page AT91SAM9260 ® , Windows CE, and Subpage Size - 16K bytes 1K byte - 53 ...
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... The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. AT91SAM9260 54 6221G–ATARM–31-Jan-08 ...
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... DCache can be enabled or disabled by writing either bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 6221G–ATARM–31-Jan-08 AT91SAM9260 55 ...
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... AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. AT91SAM9260 56 6221G–ATARM–31-Jan-08 ...
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... NCB, WT that has missed in DCache) • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT write. Full-line cache write-back, eight-word burst NCNB, NCB, WT write. Cache linefill AT91SAM9260 57 ...
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... AT91SAM9260 58 6221G–ATARM–31-Jan-08 ...
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... AT91SAM9260 Debug and Test 12.1 Description The AT91SAM9260 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...
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... Block Diagram Figure 12-1. Debug and Test Block Diagram Boundary Port ARM9EJ-S ARM926EJ-S PDC TAP: Test Access Port AT91SAM9260 60 ICE/JTAG TAP Reset and Test ICE-RT DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR TST DTXD DRXD 6221G–ATARM–31-Jan-08 ...
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... Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example 6221G–ATARM–31-Jan-08 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAM9260 Connector AT91SAM9260-based Application Board AT91SAM9260 Host Debugger Terminal 61 ...
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... Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Chip 2 Connector AT91SAM9260 Chip 1 AT91SAM9260-based Application Board In Test Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Reset Signal Test Clock Test Data In ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 6221G–ATARM–31-Jan-08 AT91SAM9260 ™ is supported via the ICE/JTAG port connected ...
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... The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associ- ated control signals. Each AT91SAM9260 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad ...
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... Table 12-2. 6221G–ATARM–31-Jan-08 AT91SAM9260 JTAG Boundary Scan Register 297 A13 296 295 A14 294 293 A15 292 291 A16 290 289 A17 288 287 A18 286 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 ...
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... AT91SAM9260 66 AT91SAM9260 JTAG Boundary Scan Register CAS D0 D1 D10 D11 D12 D13 D14 D15 NANDOE CONTROL IN/OUT INPUT/OUTPUT ...
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... Table 12-2. 6221G–ATARM–31-Jan-08 AT91SAM9260 JTAG Boundary Scan Register 224 NANDWE 223 222 NCS0 221 220 NCS1 219 218 NRD 217 216 NRST 215 214 NWR0 213 212 NWR1 211 210 NWR3 209 208 OSCSEL 207 PA0 206 205 PA1 ...
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... AT91SAM9260 68 AT91SAM9260 JTAG Boundary Scan Register PA18 PA19 PA2 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA3 PA4 PA5 CONTROL IN/OUT ...
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... Table 12-2. 6221G–ATARM–31-Jan-08 AT91SAM9260 JTAG Boundary Scan Register 151 PA6 150 149 PA7 148 147 PA8 146 145 PA9 144 143 PB0 142 141 PB1 140 139 PB10 138 137 PB11 136 135 134 133 132 131 PB14 130 ...
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... Table 12-2. 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AT91SAM9260 70 AT91SAM9260 JTAG Boundary Scan Register PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 99 PB29 98 97 PB3 96 95 PB30 94 93 PB31 92 91 PB4 90 89 ...
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... Table 12-2. 6221G–ATARM–31-Jan-08 AT91SAM9260 JTAG Boundary Scan Register 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 PC13 68 67 PC14 66 65 PC15 64 63 PC16 62 61 PC17 60 59 PC18 58 57 PC19 PC20 52 51 PC21 50 49 PC22 48 47 PC23 ...
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... Table 12-2. AT91SAM9260 72 AT91SAM9260 JTAG Boundary Scan Register 43 PC25 42 41 PC26 40 39 PC27 38 37 PC28 36 35 PC29 PC30 30 29 PC31 28 27 PC4 26 25 PC5 24 23 PC6 22 21 PC7 20 19 PC8 18 17 PC9 16 15 RAS 14 13 RTCK 12 11 SDA10 10 09 SDCK ...
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... Table 12-2. 6221G–ATARM–31-Jan-08 AT91SAM9260 JTAG Boundary Scan Register 07 SDCKE 06 05 SDWE 04 03 SHDN 02 01 TST 00 WKUP AT91SAM9260 CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL OUT OUTPUT INPUT INPUT INPUT INPUT 73 ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B13 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B1_303F. AT91SAM9260 PART NUMBER 13 12 ...
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... AT91SAM9260 Boot Program 13.1 Description The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the DataFlash Boot program is executed. It looks for a sequence of eight valid ARM excep- tion vectors in a DataFlash connected to the SPI ...
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... Crystal Table SPI DataFlash Boot No Timeout < SPI DataFlash Boot No Timeout < NAND Flash Boot No Timeout 1 s Typ. USB Enumeration Run SAM-BA Boot AT91SAM9260 76 Yes Main Oscillator Bypass No Reduced Crystal Table Yes Download from DataFlash (NPCS0) Yes Download from DataFlash (NPCS1) ...
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... Any other input frequency can be used but it prevents using the USB. crystals supported by the Boot Program. Large Crystal Table (MHz) OSCSEL = 1 3.2768 3.6864 4.9152 5.0 6.4 6.5536 8.0 9.8304 12.288 13.56 16.367667 17.734470 Booting either on USB or on DBGU is possible with any of these crystals. AT91SAM9260 18.432 Other Yes Yes Yes No 6.0 12.0 25.0 50.0 Yes Yes Yes Yes Yes ...
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... Table 13-4 defines the crystals supported by the Boot Program. Input Frequencies Supported (OSCSEL = 1) 3.2768 3.6864 4.9152 5.0 6.4 6.5536 8.0 9.8304 12.288 13.56 16.367667 17.734470 25 28.224 48.0 50.0 Booting either on USB or on DBGU is possible with any of these input frequencies. AT91SAM9260 3.84 4.0 5.24288 6.0 7.159090 7.3728 10.0 11.05920 14.31818 14.7456 18.432 20 ...
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... Scan Reduced Table (Table 15.1 &15.2) MCK = Mosc UDPCK = PLLB/2 DBGU not configured DataFlash Boot ? Yes End NANDFlash Boot ? No (USB) Autobaudrate ? MCK = Mosc UDPCK = PLLB/2 DBGU not configured End AT91SAM9260 Yes End No Yes (DBGU) MCK = PLLB UDPCK = xxxx DBGU configured End 79 ...
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... AT91SAM9260 0x0000_0000 Internal SRAM REMAP 0x0010_0000 Internal ROM B 0x20 B 0x04 B _main B 0x0c B 0x10 B 0x14 B 0x18 B 0x1c “Structure of ARM Vector 6” on page 16 15 ...
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... B 0x10 <- Code size = 4660 bytes 00001234 eafffffe B 0x18 DataFlash Device Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits AT91SAM9260 Table 13-5 summarizes the Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 528 4096 528 8192 1056 ...
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... LDR or Branch instruction Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9260 No Jump to next boot solution No 82 ...
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... Timeout Value in Seconds OSCSEL = 1 32.768 not necessary to indicate size to download in ARM vector 6 as 4096 bytes are downloaded in every case. Supported NAND Flash Manufacturers MHz (OSCSEL = 1). AT91SAM9260 OSCSEL = 0 32.768 42 1 0.78 “DataFlash Boot” on page 80 for more information Identifier 0x98 0xEC ...
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... Address, Value# read a half word Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument AT91SAM9260 No 1st measurement No 2nd measurement No Test Communication UART operational Table 13-8. Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# ...
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... CRC16 Figure 13-9 6221G–ATARM–31-Jan-08 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. : Number of bytes in hexadecimal to receive NbOfBytes to 01) shows a transmission using this protocol. AT91SAM9260 85 ...
Page 86
... ACK ® , from Windows 98SE to Windows XP. The CDC document, available at Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. AT91SAM9260 Device 86 ...
Page 87
... Used to clear or disable a specific feature. End Address 0x201000 Table 13-2 and Table 13-3 on page 77 AT91SAM9260 Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present ...
Page 88
... These pins Pin MOSI MISO SPCK NPCS0 NPCS1 NANDCS NAND Ready Busy DRXD DTXD AT91SAM9260 PIO Line PIOA1 PIOA0 PIOA2 PIOA3 PIOC11 PIOC14 PIOC13 PIOB14 PIOB15 88 ...
Page 89
... NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 6221G–ATARM–31-Jan-08 Reset Controller Startup Counter Reset State Manager user_reset NRST Manager nrst_out exter_nreset SLCK AT91SAM9260 rstc_irq proc_nreset periph_nreset backup_neset 89 ...
Page 90
... Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. AT91SAM9260 90 Figure 14-2 shows the block diagram of the NRST Manager. ...
Page 91
... VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 6221G–ATARM–31-Jan-08 XXX BMS sampling delay = 3 cycles shows how the General Reset affects the reset signals. AT91SAM9260 91 ...
Page 92
... Figure 14-4. General Reset State SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9260 92 Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset XXX BMS Sampling 6221G–ATARM–31-Jan-08 ...
Page 93
... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 6221G–ATARM–31-Jan-08 Resynch. Processor Startup 2 cycles = 3 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) AT91SAM9260 Any Freq. 0x1 = WakeUp Reset XXX 93 ...
Page 94
... ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these com- mands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. AT91SAM9260 Resynch ...
Page 95
... ERSTL. However, the resulting low level on NRST does not result in a User Reset state. 6221G–ATARM–31-Jan-08 Any Freq. Resynch. Processor Startup 1 cycle = 3 cycles XXX Any EXTERNAL RESET LENGTH AT91SAM9260 0x3 = Software Reset 8 cycles (ERSTL=2) 95 ...
Page 96
... A watchdog event is impossible because the Watchdog Timer is being reset by the – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. AT91SAM9260 96 Any Freq. Processor Startup ...
Page 97
... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6221G–ATARM–31-Jan-08 AT91SAM9260 read RSTC_SR 2 cycle resynchronization Figure 97 ...
Page 98
... Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. AT91SAM9260 98 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset Back-up Reset ...
Page 99
... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6221G–ATARM–31-Jan- KEY – – – – – – – – EXTRST AT91SAM9260 – – – PERRST – PROCRST 24 16 – 8 – ...
Page 100
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. AT91SAM9260 100 – ...
Page 101
... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6221G–ATARM–31-Jan- KEY – – – – – URSTIEN – AT91SAM9260 – – – ERSTL – – URSTEN (ERSTL+1) Slow Clock cycles. This ...
Page 102
... AT91SAM9260 102 6221G–ATARM–31-Jan-08 ...
Page 103
... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91SAM9260 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 103 ...
Page 104
... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9260 104 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 105
... Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6221G–ATARM–31-Jan-08 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only AT91SAM9260 Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 105 ...
Page 106
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9260 106 – ...
Page 107
... Returns the current value of the Real-time Timer. 6221G–ATARM–31-Jan- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV AT91SAM9260 107 ...
Page 108
... The Real-time Alarm occured since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9260 108 – ...
Page 109
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6221G–ATARM–31-Jan-08 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91SAM9260 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 109 ...
Page 110
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9260 110 6221G–ATARM–31-Jan-08 ...
Page 111
... Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9260 111 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6221G–ATARM–31-Jan-08 ...
Page 112
... Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9260 112 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6221G–ATARM–31-Jan-08 ...
Page 113
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9260 113 KEY – – – – ...
Page 114
... The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9260 114 WDDBGHLT 21 ...
Page 115
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9260 115 – ...
Page 116
... AT91SAM9260 116 6221G–ATARM–31-Jan-08 ...
Page 117
... Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis- ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). 6221G–ATARM–31-Jan-08 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM9260 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR ...
Page 118
... PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 17-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface AT91SAM9260 118 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 17-2 APB cycle ...
Page 119
... The bit PITS in PIT_SR asserts interrupt. 6221G–ATARM–31-Jan-08 Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR – – – – – PIV PIV AT91SAM9260 Access Reset Read-write 0x000F_FFFF Read-only 0x0000_0000 Read-only 0x0000_0000 Read-only 0x0000_0000 – PITIEN PITEN PIV ...
Page 120
... Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. AT91SAM9260 120 – – ...
Page 121
... Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. 6221G–ATARM–31-Jan- PICNT CPIV CPIV AT91SAM9260 CPIV 121 ...
Page 122
... AT91SAM9260 122 ...
Page 123
... The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller. 6221G–ATARM–31-Jan-08 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset RTTWK SHDW_MR SHDW_SR set AT91SAM9260 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW Type Input Output 123 ...
Page 124
... SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. AT91SAM9260 124 SHDN ...
Page 125
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6221G–ATARM–31-Jan-08 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only AT91SAM9260 Reset - 0x0000_0003 0x0000_0000 125 ...
Page 126
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9260 126 KEY – – – ...
Page 127
... Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change SHDN pin. AT91SAM9260 26 25 – – – – – — – – – ...
Page 128
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTTWK: Real-time Timer Wake- wake-up alarm from the RTT occurred since the last read of SHDW_SR least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. AT91SAM9260 128 – ...
Page 129
... AT91SAM9260 Bus Matrix 19.1 Description The Bus Matrix implements a multi-layer AHB based on the AHB-Lite protocol that enables par- allel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 6 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency) ...
Page 130
... INCR transfer. 4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). AT91SAM9260 130 130. Section 19.4.1.1 ”Undefined Length 130). 131). ...
Page 131
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). 6221G–ATARM–31-Jan-08 AT91SAM9260 131 ...
Page 132
... Priority Register A for Slave 2 0x0094 Reserved 0x0098 Priority Register A for Slave 3 0x009C Reserved 0x00A0 Priority Register A for Slave 4 0x00A8 - 0x00FC Reserved 0x0100 Master Remap Control Register 0x0104 - 0x010C Reserved AT91SAM9260 132 Name Access MATRIX_MCFG0 Read/Write MATRIX_MCFG1 Read/Write MATRIX_MCFG2 Read/Write MATRIX_MCFG3 Read/Write MATRIX_MCFG4 Read/Write MATRIX_MCFG5 Read/Write – ...
Page 133
... The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 6221G–ATARM–31-Jan- – – – – – – – – – – – – AT91SAM9260 – – – – – – – – – ULBT 133 ...
Page 134
... This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0. • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved AT91SAM9260 134 – – ...
Page 135
... Fixed priority of Master x for access to the selected slave.The higher the number, the higher the priority. 6221G–ATARM–31-Jan- – – – M5PR – M3PR – M1PR – AT91SAM9260 – – – – M4PR – M2PR – M0PR 135 ...
Page 136
... RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master AT91SAM9260 136 – – – – – ...
Page 137
... EBI D0 - D15 Data Bus bits are not internally pulled-up. • VDDIOMSEL: Memory voltage selection 6221G–ATARM–31-Jan- – – – – – – EBI_CS5A EBI_CS4A EBI_CS3A AT91SAM9260 Name Access – – EBI_CSA Read/Write – – – – – – – ...
Page 138
... Memories are 1.8V powered Memories are 3.3V powered. AT91SAM9260 138 6221G–ATARM–31-Jan-08 ...
Page 139
... AT91SAM9260 External Bus Interface 20.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI ...
Page 140
... Block Diagram 20.2.1 External Bus Interface Figure 20-1 Figure 20-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9260 140 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Static Logic Memory Controller CompactFlash Logic NAND Flash Logic ...
Page 141
... EBI_NWR0 - EBI_NWR3 Write Signals EBI_NBS0 - EBI_NBS3 Byte Mask Signals EBI_SDA10 SDRAM Address 10 Line 6221G–ATARM–31-Jan-08 EBI SMC EBI for CompactFlash Support EBI for NANDFlash Support SDRAM Controller AT91SAM9260 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 142
... The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 20-2 on page 142 EBI pins. Table 20-2. AT91SAM9260 142 details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins ...
Page 143
... A[1:21] A[1:21] A[22:24] A[22:24 ( (1) WE NUB – – AT91SAM9260 4 x 8-bit 2 x 16-bit 32-bit Static Static Static Devices Devices D15 D16 - D23 D24 - D31 (3) – NLB (2) (4) WE NLB A[0:20] A[0:20] A[21:23] A[21:23 ...
Page 144
... A21/NANDALE A22/NANDCLE A23 - A24 A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NCS6 NCS7 NANDOE NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 AT91SAM9260 144 Pins of the Interfaced Device CompactFlash SDRAM (EBI only) SDRAMC D15 D16 - D31 – DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – ...
Page 145
... CE2 CLK – CKE – RAS – CAS – WE – – WAIT – CD1 or CD2 – – – – AT91SAM9260 CompactFlash True IDE Mode NANDFlash (EBI only) SMC CS1 – – – – – – – – – – – WAIT – ...
Page 146
... It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: • the Static Memory Controller (SMC) • the SDRAM Controller (SDRAMC) AT91SAM9260 146 shows an example of connections between the EBI and external devices ...
Page 147
... FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 6221G–ATARM–31-Jan-08 AT91SAM9260 147 ...
Page 148
... Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5 address space must be set as shown in NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. AT91SAM9260 148 148. Offset 0x00E0 0000 ...
Page 149
... Access to Odd Byte on D[15:8] Don’t 1 Access to Even Byte on D[7:0] Care 1 8 bits Access to Odd Byte on D[7:0] 1 – demonstrates a schematic representation of this logic. AT91SAM9260 SMC Access Mode Byte Select Byte Select Byte Select Byte Select Don’t Care – – Figure 149 ...
Page 150
... EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in responding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1). Table 20-8. Dedicated CompactFlash Interface Multiplexing Pins CS4A = 1 NCS4/CFCS0 CFCS0 NCS5/CFCS1 AT91SAM9260 150 CompactFlash Logic A23 A22 ...
Page 151
... Memory Controller (SMC)”. 6221G–ATARM–31-Jan-08 Access to CompactFlash Device CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW illustrates an example of a CompactFlash application. CFCS0 and AT91SAM9260 Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 151 ...
Page 152
... Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User Inter- face to the appropriate value enables the NANDFlash logic. For details on this register, refer to the section “AT91SAM9260 Bus Matrix”. Access to an external NANDFlash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF) ...
Page 153
... Figure 20-7. NANDFlash Application Example EBI PIO PIO 6221G–ATARM–31-Jan-08 NAND Flash Logic NCSx NRD_NOE D[7:0] A[22:21] NCSx/NANDCS Not Connected NANDOE NANDWE AT91SAM9260 NANDOE NANDOE NANDWE NANDWE AD[7:0] ALE CLE NAND Flash NOE NWE CE R/B 153 ...
Page 154
... Note: 20.7 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. AT91SAM9260 154 The External Bus Interface is also able to support 16-bit devices. 6221G–ATARM–31-Jan-08 ...
Page 155
... SDCK CLK NBS0 A0 15 DQML NBS1 39 CFIOR_NBS1_NWR1 DQMH CAS 17 CAS CAS RAS 18 RAS RAS SDWE 16 SDWE WE 19 SDCS_NCS1 CS 256 Mbits TSOP54 PACKAGE AT91SAM9260 D0 2 DQ0 D1 4 DQ1 D2 5 DQ2 D3 7 DQ3 D4 8 DQ4 D5 10 DQ5 D6 11 DQ6 D7 13 DQ7 D8 42 DQ8 ...
Page 156
... The Data Bus Width programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the “SDRAM device initialisation” part of the SDRAM controller. AT91SAM9260 156 ...
Page 157
... NANDFlash timings, the data bus width and the system bus frequency. 6221G–ATARM–31-Jan- 10K 10K 3V3 R2 R2 10K 10K AT91SAM9260 K9F2G08U0M K9F2G08U0M D0 29 CLE I/ ALE R ...
Page 158
... Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 20.7.4.2 Software Configuration The software configuration is the same as for an 8-bit NANDFlash except the data bus width programmed in the mode register of the Static Memory Controller. AT91SAM9260 158 CLE 17 ALE ...
Page 159
... A17 A19 16 AT49BV6416 AT49BV6416 A18 A20 15 A19 A21 10 A20 A22 9 A21 VCCQ 12 RESET 3V3 VPP TSOP48 PACKAGE AT91SAM9260 D0 29 DQ0 D1 31 DQ1 D2 33 DQ2 D3 35 DQ3 D4 38 DQ4 D5 40 DQ5 D6 42 DQ6 D7 44 DQ7 D8 30 DQ8 D9 32 ...
Page 160
... A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT AT91SAM9260 160 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 ...
Page 161
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 6221G–ATARM–31-Jan-08 AT91SAM9260 161 ...
Page 162
... A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT AT91SAM9260 162 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 ...
Page 163
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 6221G–ATARM–31-Jan-08 AT91SAM9260 163 ...
Page 164
... AT91SAM9260 164 6221G–ATARM–31-Jan-08 ...
Page 165
... Write or Byte Select Access” on page 167 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page Byte-write or byte-select access, see Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 167 AT91SAM9260 Type Output Output Output Output Output ...
Page 166
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other putposes by the PIO Controller. AT91SAM9260 166 128K x 8 SRAM ...
Page 167
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6221G–ATARM–31-Jan-08 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-5 AT91SAM9260 Figure 21-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 168
... Figure 21-3. Memory Connection for an 8-bit Data Bus Figure 21-4. Memory Connection for a 16-bit Data Bus Figure 21-5. Memory Connection for a 32-bit Data Bus SMC AT91SAM9260 168 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] D[31:16] D[15:0] A[20:2] NBS0 NBS1 NBS2 NBS3 NWE NRD NCS[2] ...
Page 169
... Byte Select Access is used to connect two 16-bit devices. Figure 21-7 mode, on NCS3 (BAT = Byte Select Access). 6221G–ATARM–31-Jan-08 Figure 21-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access AT91SAM9260 169 ...
Page 170
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9260 170 D[7:0] D[15:8] ...
Page 171
... Bus 2x16-bit 4 x 8-bit Byte Select Byte Write NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 AT91SAM9260 D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable ...
Page 172
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91SAM9260 172 Figure 21-8. NRD_SETUP NRD_PULSE ...
Page 173
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 21.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6221G–ATARM–31-Jan-08 AT91SAM9260 Figure 21-9). 173 ...
Page 174
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91SAM9260 174 NRD_PULSE NRD_PULSE ...
Page 175
... Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 6221G–ATARM–31-Jan-08 t PACC Data Sampling shows the typical read cycle of an LCD module. The read data is valid t t PACC Data Sampling AT91SAM9260 after PACC 175 ...
Page 176
... NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NCS_WR_SETUP AT91SAM9260 176 NWE_SETUP NWE_PULSE NCS_WR_PULSE NWE_CYCLE Figure 21-12. The write cycle NWE_HOLD NCS_WR_HOLD 6221G–ATARM–31-Jan-08 ...
Page 177
... NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 21.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6221G–ATARM–31-Jan-08 NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE AT91SAM9260 Figure 21-13). How- NWE_PULSE NCS_WR_PULSE NWE_CYCLE 177 ...
Page 178
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91SAM9260 178 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is shows the waveforms of a write operation with WRITE_MODE set to 0. The data is 6221G– ...
Page 179
... Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] AT91SAM9260 Permitted Range Coded Value Effective Value 0 ≤ ≤ 31 128 ≤ ≤ 128+31 0 ≤ ≤ 63 256 ≤ ...
Page 180
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 21-16 Select 2. AT91SAM9260 180 gives the default value of timing parameters at reset. Reset Values of Timing Parameters Reset Value ...
Page 181
... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 6221G–ATARM–31-Jan-08 NRD_CYCLE Read to Write Wait State (Figure 21-17). Figure AT91SAM9260 NWE_CYCLE Chip Select Wait State 21-19. (Figure 181 ...
Page 182
... D[31:0] Figure 21-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91SAM9260 182 no hold write cycle Early Read wait state no hold write cycle Early Read (READ_MODE = 0 or READ_MODE = 1) (WRITE_MODE = 0) ...
Page 183
... A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see 6221G–ATARM–31-Jan-08 MCK no hold NRD write cycle Early Read (WRITE_MODE = 1) wait state AT91SAM9260 read setup = 1 read cycle (READ_MODE = 0 or READ_MODE = 1) “Slow Clock Mode” on page 195). 183 ...
Page 184
... SMC accesses. This wait cycle is referred read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See AT91SAM9260 184 Figure 21-16 on page 181. 6221G–ATARM–31-Jan-08 ...
Page 185
... NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 6221G–ATARM–31-Jan-08 ) for each external memory device is programmed in the DF will not slow down the execution of a program from internal DF illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), AT91SAM9260 Figure 21-21 shows the read oper- 185 ...
Page 186
... NBS2, NBS3, A0, A1 NRD NCS D[31:0] Figure 21-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS D[31:0] AT91SAM9260 186 tpacc TDF = 2 clock cycles NRD controlled read operation tpacc TDF = 3 clock cycles NCS controlled read operation 6221G–ATARM–31-Jan-08 ...
Page 187
... TDF optimization. 6221G–ATARM–31-Jan-08 shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 TDF_CYCLES = 6 Read to Write Wait State 21-23, Figure 21-24 and Figure 21-25 AT91SAM9260 NWE_SETUP= 3 write access on NCS0 (NWE controlled) illustrate the cases: 187 ...
Page 188
... A NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 cycle TDF_CYCLES = 4 AT91SAM9260 188 read1 hold = 1 TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State ...
Page 189
... The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 6221G–ATARM–31-Jan-08 read1 hold = 1 TDF_CYCLES = 5 read1 cycle Read to Write Wait State (“Asynchronous Page Mode” on page 195). AT91SAM9260 write2 setup = 1 4 TDF WAIT STATES write2 cycle TDF_MODE = 0 (optimization disabled) 198 Slow Clock Mode 189 ...
Page 190
... The assertion of the NWAIT signal outside the expected period is ignored as illustrated in 21-27. Figure 21-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9260 190 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 1 ...
Page 191
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6221G–ATARM–31-Jan-08 FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 AT91SAM9260 Assertion is ignored 0 0 191 ...
Page 192
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 6221G–ATARM–31-Jan- Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 AT91SAM9260 Figure 21-28 and Figure 21-29. After Wait STATE Fig- 192 ...
Page 193
... Figure 21-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6221G–ATARM–31-Jan- Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 AT91SAM9260 Wait STATE Assertion is ignored 193 ...
Page 194
... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 21-30. NWAIT Latency MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal 6221G–ATARM–31-Jan- minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 AT91SAM9260 WAIT STATE Fig- 194 ...
Page 195
... They are valid on all Table 21-6 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode Duration (cycles AT91SAM9260 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ ...
Page 196
... NWE_CYCLE = 3 SLOW CLOCK MODE WRITE AT91SAM9260 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State ...
Page 197
... Figure 21-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE 6221G–ATARM–31-Jan- IDLE STATE AT91SAM9260 NORMAL MODE WRITE Reload Configuration Wait State 197 ...
Page 198
... A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored. shows the NRD and NCS timings in page mode access. tpa NRD_PULSE NCS_RD_PULSE AT91SAM9260 Table 21-7. ) takes longer than the subse- pa Figure 21-34 ...
Page 199
... Access time of subsequent accesses in the page sa ‘x’ No impact ) and the NRD_PULSE for accesses to the page ( shorter than the programmed value for Figure 21- AT91SAM9260 Table 21- Table 21-7 are identical, then the cur- illustrates access to an 8-bit memory device in ), even if sa 199 ...
Page 200
... Figure 21-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6221G–ATARM–31-Jan-08 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9260 NRD_PULSE 200 ...