LPC2103FBD48 NXP Semiconductors, LPC2103FBD48 Datasheet
LPC2103FBD48
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LPC2103FBD48 Summary of contents
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LPC2101/2102/2103 Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC Rev. 02 — 18 December 2007 1. General description The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines ...
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... Processor wake-up from Power-down mode via external interrupt or RTC. 3. Ordering information Table 1. Type number LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2103FA44 3.1 Ordering options Table 2. Type number LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2103FA44 LPC2101_02_03_2 Preliminary data sheet Ordering information Package Name Description LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 LQFP48 plastic low profi ...
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... NXP Semiconductors 4. Block diagram LPC2101/2102/2103 HIGH SPEED P0[31:0] GENERAL PURPOSE I/O BOOT ROM ARM7 local bus INTERNAL SRAM CONTROLLER 2 kB/4 kB SRAM EINT2 to EXTERNAL (1) EINT0 INTERRUPTS (1) 3 CAP0 (1) 4 CAP1 CAPTURE/COMPARE (1) 3 CAP2 EXTERNAL COUNTER (1) 3 MAT0 TIMER 0/TIMER 1/ (1) 4 MAT1 TIMER 2/TIMER 3 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1 P0.29/TCK/CAP2.2 Fig 2. LQFP48 pin configuration LPC2101_02_03_2 Preliminary data sheet VBAT 5 V DD(1V8) RST 6 LPC2101/2102/2103 XTAL1 12 XTAL2 Rev. 02 — 18 December 2007 LPC2101/2102/2103 Single-chip 16-bit/32-bit microcontrollers 36 P0 ...
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... NXP Semiconductors P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 P0.27/TRST/CAP2.0 Fig 3. PLCC44 pin configuration LPC2101_02_03_2 Preliminary data sheet DD(1V8) 11 RST LPC2101/2102/2103 P0.28/TMS/CAP2.1 15 P0.29/TCK/CAP2.2 XTAL1 16 XTAL2 17 Rev. 02 — 18 December 2007 LPC2101/2102/2103 Single-chip 16-bit/32-bit microcontrollers 39 P0.11/CTS1/CAP1.1/AD0.4 38 P0.10/RTS1/CAP1.0/AD0 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol LQFP48 P0.0 to P0.31 [1] P0.0/TXD0/ 13 MAT3.1 [2] P0.1/RXD0/ 14 MAT3.2 [3] P0.2/SCL0/ 18 CAP0.0 [3] P0.3/SDA0/ 21 MAT0.0 [4] P0.4/SCK0/ 22 CAP0.1 [4] P0.5/MISO0/ 23 MAT0.1 [4] P0.6/MOSI0/ 24 CAP0.2 [2] P0.7/SSEL0/ 28 MAT2.0 [4] P0.8/TXD1/ 29 MAT2.1 [2] P0.9/RXD1/ 30 MAT2.2 LPC2101_02_03_2 Preliminary data sheet PLCC44 Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol LQFP48 [4] P0.10/RTS1/ 35 CAP1.0/AD0.3 [3] P0.11/CTS1/ 36 CAP1.1/AD0.4 [4] P0.12/DSR1/ 37 MAT1.0/AD0.5 [4] P0.13/DTR1/ 41 MAT1.1 [3] P0.14/DCD1/ 44 SCK1/EINT1 [4] P0.15/RI1/ 45 EINT2 [2] P0.16/EINT0/ 46 MAT0.2 [1] P0.17/CAP1.2/ 47 SCL1 [1] P0.18/CAP1.3/ 48 SDA1 [1] P0.19/MAT1.2/ 1 MISO1 [2] P0.20/MAT1.3/ 2 MOSI1 LPC2101_02_03_2 Preliminary data sheet PLCC44 Type Description [4] 38 I/O P0.10 — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol LQFP48 [4] P0.21/SSEL1/ 3 MAT3.0 [4] P0.22/AD0.0 32 [1] P0.23/AD0.1 33 [1] P0.24/AD0.2 34 [1] P0.25/AD0.6 38 [1] P0.26/AD0.7 39 [4] P0.27/TRST/ 8 CAP2.0 [4] P0.28/TMS/ 9 CAP2.1 [4] P0.29/TCK/ 10 CAP2.2 [4] P0.30/TDI/ 15 MAT3.3 [4] P0.31/TDO 16 [5] RTCX1 20 [5] RTCX2 25 [5] RTCK 26 XTAL1 11 XTAL2 12 DBGSEL 27 LPC2101_02_03_2 Preliminary data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol LQFP48 RST 19 SSA V 42 DDA V 5 DD(1V8) V 17, 40 DD(3V3) VBAT 4 [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input function, this pad utilizes built-in glitch fi ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC) ...
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... NXP Semiconductors 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/2102/2103 provide 2 kB static RAM. 6.4 Memory map The LPC2101/2102/2103 memory map incorporates several distinct regions, as shown in Figure 4 ...
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... NXP Semiconductors 6.5 Interrupt controller The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. ...
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... NXP Semiconductors 6.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins ...
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... NXP Semiconductors • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware fl ...
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... NXP Semiconductors • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.12 SSP serial I/O controller The LPC2101/2102/2103 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus ...
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... NXP Semiconductors – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.14 General purpose 16-bit timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt ...
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... NXP Semiconductors • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T T PCLK 6.16 Real-time clock The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode) ...
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... NXP Semiconductors 6.17.3 Reset and wake-up timer Reset has two sources on the LPC2101/2102/2103: the RST pin and watchdog reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fi ...
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... NXP Semiconductors 6.17.7 Power control The LPC2101/2102/2103 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses ...
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... NXP Semiconductors entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V analog input voltage IA V input voltage I I supply current ...
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... NXP Semiconductors 8. Static characteristics Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog 3.3 V pad supply DDA voltage V input voltage on pin VBAT i(VBAT) Standard port pins, RST, RTCK ...
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... NXP Semiconductors Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I Power-down mode battery BATpd [12] supply current I active mode battery BATact [12] supply current 2 I C-bus pins V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage ...
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... NXP Semiconductors Table 6. ADC static characteristics +85 C unless otherwise specified. ADC frequency 4.5 MHz. DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 9. Dynamic characteristics Table 7. Dynamic characteristics for commercial applications +85 C for industrial applications, V amb [1] specified ranges . Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX ...
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... NXP Semiconductors 10. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 11. Abbreviations Table 8. Acronym ADC AMBA APB DCC DSP FIFO FIQ GPIO IAP IRQ ISP PLL PWM SPI SRAM SSI SSP TTL UART VIC LPC2101_02_03_2 Preliminary data sheet Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus ...
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... Release date LPC2101_02_03_2 20071218 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • pins SDA1 and SCL1 pad characteristics corrected: These pins are not open-drain. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 10 6.1 Architectural overview 6.2 On-chip flash program memory . . . . . . . . . . . 10 6.3 On-chip static RAM 6.4 Memory map 6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12 6.5.1 Interrupt sources ...