74AHC126PW,118 NXP Semiconductors, 74AHC126PW,118 Datasheet - Page 9

IC BUFF DVR TRI-ST QD 14TSSOP

74AHC126PW,118

Manufacturer Part Number
74AHC126PW,118
Description
IC BUFF DVR TRI-ST QD 14TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCr
Datasheets

Specifications of 74AHC126PW,118

Package / Case
14-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AHC
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
11.5 ns @ 3 V to 3.6 V or 7.5 ns @ 4.5 V to 5.5 V
Number Of Lines (input / Output)
4 / 4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AHC126PW-T
74AHC126PW-T
935262769118
NXP Semiconductors
Table 8.
Table 9.
74AHC_AHCT126_3
Product data sheet
Type
74AHC126
74AHCT126
Type
74AHC126
74AHCT126
Fig 7.
Test data is given in
Definitions test circuit:
R
C
R
S1 = test selection switch.
Test circuitry for measuring switching times
T
L
L
Measurement points
Test data
= termination resistance should be equal to output impedance Z
= load capacitance including jig and probe capacitance.
= load resistance.
Input
V
V
3.0 V
I
CC
Table
Input
V
0.5
1.5 V
M
negative
positive
t
9.
r
, t
pulse
pulse
3.0 ns
3.0 ns
V
0 V
0 V
f
CC
V
V
G
I
I
90 %
10 %
V I
Load
C
15 pF, 50 pF
15 pF, 50 pF
L
t
t
f
r
V
V
Rev. 03 — 25 April 2008
M
M
R T
10 %
90 %
Output
V
0.5
0.5
M
DUT
V
CC
V
V
CC
CC
t
t
W
W
R
1 k
1 k
V O
L
74AHC126; 74AHCT126
o
of the pulse generator.
V
V
M
M
C L
t
t
r
f
R L
V
V
V
S1 position
t
open
open
PHL
X
OL
OL
, t
+ 0.3 V
+ 0.3 V
S1
PLH
001aad983
V
CC
Quad buffer/line driver; 3-state
open
t
GND
GND
PZH
, t
PHZ
V
V
V
Y
OH
OH
© NXP B.V. 2008. All rights reserved.
0.3 V
0.3 V
t
V
V
PZL
CC
CC
, t
PLZ
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