74LV125PW,118 NXP Semiconductors, 74LV125PW,118 Datasheet - Page 7

IC BUFF DVR TRI-ST QUAD 14TSSOP

74LV125PW,118

Manufacturer Part Number
74LV125PW,118
Description
IC BUFF DVR TRI-ST QUAD 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet

Specifications of 74LV125PW,118

Package / Case
14-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
16mA, 16mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LV
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 16 mA
Input Bias Current (max)
160 uA
Low Level Output Current
16 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
55 ns (Typ) @ 1.2 V or 19 ns (Typ) @ 2 V or 14 ns (Typ) @ 2.7 V or 10 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
4 / 4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LV125PW-T
74LV125PW-T
935174350118
NXP Semiconductors
Table 8.
74LV125_3
Product data sheet
Supply voltage
V
< 2.7 V
2.7 V to 3.6 V
Fig 7.
CC
4.5 V
Measurement points are given in
V
Enable and disable times
OL
Measurement points
and V
OH
are typical voltage output levels that occur with the output load.
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Input
V
0.5V
1.5 V
0.5V
nOE input
output
M
output
CC
CC
GND
GND
V
V
V
Table
OH
CC
OL
V
I
8.
V
M
Rev. 03 — 7 April 2009
enabled
outputs
t
PLZ
t
Output
V
0.5V
1.5 V
0.5V
PHZ
M
CC
CC
V
X
V
Y
disabled
outputs
V
V
V
V
t
PZL
t
X
OL
OL
OL
PZH
+ 0.1V
+ 0.3 V
+ 0.1V
V
M
V
Quad buffer/line driver; 3-state
M
CC
CC
outputs
enabled
mna362
V
V
V
V
Y
OH
OH
OH
© NXP B.V. 2009. All rights reserved.
74LV125
0.1V
0.3 V
0.1V
CC
CC
7 of 15

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