74LV125PW,112 NXP Semiconductors, 74LV125PW,112 Datasheet - Page 12

IC BUFF DVR TRI-ST QUAD 14TSSOP

74LV125PW,112

Manufacturer Part Number
74LV125PW,112
Description
IC BUFF DVR TRI-ST QUAD 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet

Specifications of 74LV125PW,112

Package / Case
14-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
16mA, 16mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
74LV
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 16 mA
Input Bias Current (max)
160 uA
Low Level Output Current
16 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
9 ns
Number Of Lines (input / Output)
4 / 4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4596-5
74LV125PW
74LV125PW
935174350112
NXP Semiconductors
Fig 12. Package outline SOT402-1 (TSSOP14)
74LV125_3
Product data sheet
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT402-1
max.
1.1
A
0.15
0.05
A
1
0.95
0.80
14
A
1
2
y
IEC
Z
0.25
pin 1 index
A
e
3
D
0.30
0.19
b
p
MO-153
JEDEC
0.2
0.1
c
b
p
8
7
REFERENCES
D
5.1
4.9
0
(1)
Rev. 03 — 7 April 2009
w
M
E
4.5
4.3
(2)
JEITA
scale
2.5
0.65
e
c
A
H
6.6
6.2
2
E
A
1
5 mm
L
1
0.75
0.50
L
H
p
E
E
detail X
0.4
0.3
Q
L
Quad buffer/line driver; 3-state
L
PROJECTION
EUROPEAN
p
0.2
v
Q
A
(A )
0.13
3
w
X
v
0.1
A
© NXP B.V. 2009. All rights reserved.
y
M
74LV125
ISSUE DATE
A
99-12-27
03-02-18
0.72
0.38
Z
(1)
SOT402-1
8
0
o
o
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