IDT71V124S15Y Integrated Device Technology, Inc., IDT71V124S15Y Datasheet
IDT71V124S15Y
Manufacturer Part Number
IDT71V124S15Y
Description
Manufacturer
Integrated Device Technology, Inc.
Specifications of IDT71V124S15Y
Case
SOJ
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Features
Functional Block Diagram
©2000 Integrated Device Technology, Inc.
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Commercial (0°C to +70°C) and Industrial (–40°C to
+85°C) temperature options
Equal access and cycle times
— Industrial and Commercial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Available in 32-pin 400 mil Plastic SOJ.
I/O
0
- I/O
A
A
16
7
0
WE
OE
CS
•
•
•
8
ADDRESS
DECODER
8
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
CONTROL
LOGIC
1
Description
nized as 128K x 8. It is fabricated using IDT’s high-performance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs. The JEDEC center
power/GND pinout reduces noise generation and improves system
performance.
7ns, with address access times as fast as 15ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
•
•
•
The IDT71V124 is a 1,048,576-bit high-speed static RAM orga-
The IDT71V124 has an output enable pin which operates as fast as
The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ.
MEMORY ARRAY
I/O CONTROL
1,048,576-BIT
3484 drw 01
AUGUST 2000
IDT71V124
8
DSC-3484/05
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