IDT71V124S15Y Integrated Device Technology, Inc., IDT71V124S15Y Datasheet
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IDT71V124S15Y
Manufacturer Part Number
IDT71V124S15Y
Description
Manufacturer
Integrated Device Technology, Inc.
Specifications of IDT71V124S15Y
Case
SOJ
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©2000- Integrated Device Technology, Inc.
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
I/O
0
- I/O
A
A
16
7
0
WE
OE
CS
•
•
•
8
ADDRESS
DECODER
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
8
CONTROL
LOGIC
•
•
•
1
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
The IDT71V124 has an output enable pin which operates as fast as
MEMORY ARRAY
I/O CONTROL
1,048,576-BIT
3873 drw 01
IDT71V124SA
8
.
DSC-3873/05