74AHCT2G125DP,125 NXP Semiconductors, 74AHCT2G125DP,125 Datasheet

IC BUFF DVR TRI-ST DL 8TSSOP

74AHCT2G125DP,125

Manufacturer Part Number
74AHCT2G125DP,125
Description
IC BUFF DVR TRI-ST DL 8TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCTr
Datasheet

Specifications of 74AHCT2G125DP,125

Package / Case
8-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AHCT
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 8 mA
Input Bias Current (max)
1 uA
Low Level Output Current
8 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
7.5 ns @ 5 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AHCT2G125DP-G
74AHCT2G125DP-G
935274675125
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74AHC2G125DP
74AHCT2G125DP
74AHC2G125DC
74AHCT2G125DC
74AHC2G125GD
74AHCT2G125GD
Ordering information
Package
Temperature range Name
The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They
provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is
controlled by the output enable input (nOE). A HIGH at nOE causes the output to assume
a high-impedance OFF-state.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
I
I
I
I
I
I
I
40 C to +125 C
40 C to +125 C
40 C to +125 C
74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state
Rev. 02 — 22 December 2008
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Multiple package options
ESD protection:
Specified from 40 C to +125 C
N
N
N
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
TSSOP8
VSSOP8 plastic very thin shrink small outline package;
XSON8U plastic extremely thin small outline package; no
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
8 leads; body width 2.3 mm
leads; 8 terminals; UTLP based; body 3
mm
Product data sheet
2
0.5
Version
SOT505-2
SOT765-1
SOT996-2

Related parts for 74AHCT2G125DP,125

74AHCT2G125DP,125 Summary of contents

Page 1

Dual buffer/line driver; 3-state Rev. 02 — 22 December 2008 1. General description The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by ...

Page 2

... NXP Semiconductors 4. Marking Table 2. Marking codes Type number 74AHC2G125DP 74AHCT2G125DP 74AHC2G125DC 74AHCT2G125DC 74AHC2G125GD 74AHCT2G125GD 5. Functional diagram 1OE 2OE mce185 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74AHC2G125 74AHCT2G125 1 1OE GND 4 001aaj260 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74AHC_AHCT2G125_2 Product data sheet 74AHC2G125 ...

Page 3

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin 1OE, 2OE GND 4 1Y Functional description [1] Table 4. Function table Control nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V) ...

Page 5

... NXP Semiconductors Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance 74AHCT2G125 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 OFF-state output current input leakage GND current 5.5 V ...

Page 6

... NXP Semiconductors Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter Conditions t enable time nOE to nY; see disable time nOE to nY; see dis power per buffer; PD dissipation pF capacitance V = GND 74AHCT2G125 t propagation nA to nY; see pd delay ...

Page 7

... NXP Semiconductors Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter Conditions C power per buffer; PD dissipation pF capacitance V = GND [ the same as t and PLH PHL t is the same as t and PZL PZH t is the same as t and t . dis PLZ ...

Page 8

... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 7. Enable and disable times Table 9. Measurement points Type Input V M 74AHC2G125 0.5V 74AHCT2G125 1.5 V 74AHC_AHCT2G125_2 Product data sheet 74AHC2G125; 74AHCT2G125 GND t PLZ V CC ...

Page 9

... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Test circuit for measuring switching times Table 10. Test data Type Input ...

Page 10

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 11. Package outline SOT996-2 (XSON8U) ...

Page 13

... Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74AHC2G125GD and 74AHCT2G125GD (XSON8U package). ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 14 Abbreviations ...

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