74LVC2G17GM,115 NXP Semiconductors, 74LVC2G17GM,115 Datasheet - Page 3
![IC BUFF SCHMT TRG DL N-INV 6XSON](/photos/1/39/13915/6-xson_sot886_pkg_sml.jpg)
74LVC2G17GM,115
Manufacturer Part Number
74LVC2G17GM,115
Description
IC BUFF SCHMT TRG DL N-INV 6XSON
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC2G17GW125.pdf
(19 pages)
Specifications of 74LVC2G17GM,115
Package / Case
6-XSON (Micropak™), SOT-886
Logic Type
Schmitt Trigger - Buffer, Driver
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
1.65 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
40 uA
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Propagation Delay Time
3.8 ns (Typ) @ 2.7 V or 3.6 ns (Typ) @ 3.3 V or 2.7 ns (Typ) @ 5 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC2G17GM-G
74LVC2G17GM-G
935277163115
74LVC2G17GM-G
935277163115
NXP Semiconductors
7. Pinning information
Table 3.
8. Functional description
Table 4.
[1]
74LVC2G17
Product data sheet
Symbol
1A
GND
2A
2Y
V
1Y
Input
nA
L
H
Fig 3.
Fig 4.
CC
H = HIGH voltage level; L = LOW voltage level.
GND
1A
2A
and SOT457
Logic diagram
Pin configuration SOT363
Pin description
Function table
1
2
3
74LVC2G17
7.1 Pinning
7.2 Pin description
001aaf078
Pin
1
2
3
4
5
6
[1]
6
5
4
1Y
V
2Y
CC
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
1A
2A
All information provided in this document is subject to legal disclaimers.
Fig 5.
GND
Rev. 5 — 6 August 2010
Pin configuration SOT886
1A
2A
Transparent top view
Dual non-inverting Schmitt trigger with 5 V tolerant input
74LVC2G17
1
2
3
Output
nY
L
H
001aaf079
6
5
4
1Y
V
2Y
CC
mnb068
1Y
2Y
Fig 6.
GND
Pin configuration SOT891,
SOT1115 and SOT1202
1A
2A
Transparent top view
74LVC2G17
74LVC2G17
1
2
3
© NXP B.V. 2010. All rights reserved.
001aaf080
6
5
4
1Y
V
2Y
CC
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