74LVT16543ADGG,112 NXP Semiconductors, 74LVT16543ADGG,112 Datasheet - Page 2

• Manufacturer Part Number: 74LVT16543ADGG,112
• Description: IC REGISTERED TXRX 16BIT 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr

Specifications of 74LVT16543ADGG,112

• Logic Type: Registered Transceiver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVT16543ADG; 74LVT16543ADG; 935203040112

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
LOGIC SYMBOL (IEEE/IEC)
1998 Feb 19
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
SYMBOL
16-bit universal bus interface
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
3.3V 16-bit registered transceiver (3-State)
I
t
t
C
C
PLH
PHL
CCZ
I/O
IN
PACKAGES
Propagation delay
nAx to nBx or nBx to nAx
Input capacitance control pins
I/O pin capacitance
Total supply current
PARAMETER
56
54
55
10
12
13
14
5
6
8
9
1
3
2
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
1EN3 (BA)
G1
1C5
2EN4 (AB)
G2
2C6
6 D
3
5 D
4
C
V
V
Outputs disabled; V
Outputs disabled; V
CC
I
L
52
51
49
48
47
45
44
43
= 0V or 3.0V
OUTSIDE NORTH AMERICA
= 50pF;
= 3.3V
2
74LVT16543A DGG
74LVT16543A DL
15
16
17
19
20
21
23
24
29
31
30
28
26
27
DESCRIPTION
The 74LVT16543A is a high-performance BiCMOS product
designed for V
8-bit transceivers or one 16-bit transceiver.
The 74LVT16543A contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB) input and the A-to-B Latch
Enable (nLEAB) input are Low, the A-to-B path is transparent.
A subsequent Low-to-High transition of the nLEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With nEAB and nOEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA,
nLEBA, and nOEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
T
amb
CONDITIONS
= 25 C; GND = 0V
7EN9 (BA)
G7
7C11
8EN10 (AB)
G8
8C12
12 D
I/O
CC
9
= 0V or 3.0V
= 3.6V
CC
operation at 3.3V. The device can be used as two
10
11 D
SW00151
NORTH AMERICA
VT16543A DGG
VT16543A DL
42
41
40
38
37
36
34
33
74LVT16543A
TYPICAL
Product specification
2.2
70
3
9
DWG NUMBER
853–1764 18986
SOT371-1
SOT364-1
UNIT
pF
pF
ns
A