M25P32-VMP6TP Numonyx, B.V., M25P32-VMP6TP Datasheet - Page 25

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M25P32-VMP6TP

Manufacturer Part Number
M25P32-VMP6TP
Description
32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
Manufacturer
Numonyx, B.V.
Datasheet
M25P32
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/V
(W/V
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
PP
) signal allow the device to be put in the Hardware Protected mode (when the Status
PP
sequence
0
High Impedance
) signal. The Status Register Write Disable (SRWD) bit and Write Protect
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
4
PP
3
) is driven Low). In
2
1
Instructions
0
7
AI02031E
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