M25PE20-VMP6TP Numonyx, B.V., M25PE20-VMP6TP Datasheet - Page 14

• Manufacturer Part Number: M25PE20-VMP6TP
• Description: 1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
• Manufacturer: Numonyx, B.V.

Operating features
4.7
4.8
4.8.1
14/64
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains two status bits that can be read by the Read Status Register
(RDSR) instruction. See
description of the Status Register bits.
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25PE10 and M25PE20 feature the following data protection mechanisms:
Protocol-related protections
●
●
●
●
●
Power On Reset and an internal timer (t
changes while the power supply is outside the operating specification
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
Section 6.5: Write Status Register
Section 6.10: Page Program
Erase
after a Reset Low pulse
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction completion
Page Erase (PE) instruction completion
SubSector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
(SE), and
Section 6.13: SubSector Erase
Section 6.4: Read Status Register (RDSR)
(PP),
Section 6.12: Page Erase
(WRSR),
PUW
) can provide protection against inadvertent
Section 6.9: Page Write
(SSE), and to
(PE),
Table 14: Device status
for a detailed
M25PE20, M25PE10
Section 6.14: Sector
(PW),