M25PX64-SOVME6E Numonyx, B.V., M25PX64-SOVME6E Datasheet - Page 47

• Manufacturer Part Number: M25PX64-SOVME6E
• Description: 64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface
• Manufacturer: Numonyx, B.V.

M25PX64
6.14
Write to lock register (WRLR)
The write to lock register (WRLR) instruction allows bits to be changed in the lock registers.
Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded, the device sets the
write enable latch (WEL).
The write to lock register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the targeted
sector and one data byte on serial data input (DQ0). The instruction sequence is shown in
Figure
latched in, otherwise the write to lock register (WRLR) instruction is not executed.
Lock register bits are volatile, and therefore do not require time to be written. When the write
to lock register (WRLR) instruction has been successfully executed, the write enable latch
(WEL) bit is reset after a delay time less than t
Any write to lock register (WRLR) instruction, while an erase, program or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 22. Write to lock register (WRLR) instruction sequence
Table 10.
1. Values of (b1, b0) after power-up are defined in
All sectors
S
C
DQ0
22. Chip Select (S) must be driven High after the eighth bit of the data byte has been
Sector
Lock register in
0
1
2
Instruction
3
4
b7-b2
Bit
b1
b0
5
(1)
6
7
Sector lock down bit value (refer to
Sector write lock bit value (refer to
MSB
23
8
22 21
9 10
24-bit address
Section 7: Power-up and
SHSL
3
28 29 30 31 32 33 34 35
2
minimum value.
1
0
MSB
7
Value
‘0’
6
power-down.
Lock register
5
Table
Table
4
in
3
36 37 38
9)
9)
2
1
Instructions
0
39
AI13740
47/66