MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 58

• Manufacturer Part Number: MSC8103
• Description: Network Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Physical and Electrical Specifications
2.6.5.2 DMA Data Transfers
Table 2-18 describes the DMA signal timing.
The DREQ
To achieve fast response, a synchronized peripheral should assert
Figure 2-11 shows synchronous peripheral interaction.
2.6.6
2-18
Number
Number
44a
44b
44c
45
46
47
72
73
74
75
76
signal is synchronized with the falling edge of
Read data strobe minimum assertion width
HACK read minimum assertion width
Read data strobe minimum deassertion width
HACK read minimum deassertion width
Read data strobe minimum deassertion width
reads
HACK minimum deassertion width after “Last Data Register” reads
Write data strobe minimum assertion width
HACK write minimum assertion width
Write data strobe minimum deassertion width
HACK write minimum deassertion width after ICR, CVR and Data Register
writes
Host data input minimum set-up time before write data strobe deassertion
Host data input minimum set-up time before HACK write deassertion
HDI16 Signals
DREQ set-up time before DLLIN falling edge
DREQ hold time after DLLIN falling edge
DONE set-up time before DLLIN rising edge
DONE hold time after DLLIN rising edge
DACK/DRACK/DONE delay after DLLIN rising edge
5,6
5
, or between two consecutive CVR, ICR, or ISR reads
DACK/DONE/DRACK Outputs
MSC8103 Network Digital Signal Processor, Rev. 12
Table 2-19.
Characteristics
Characteristic
DONE Input
Figure 2-11.
Table 2-18.
DLLIN
DREQ
8
4
Host Interface (HDI16) Timing
8
4
4
after “Last Data Register”
3
74
DLLIN
DMA Signals
DMA Signals
7
.
DONE
DREQ
5,6
timing is relative to the rising edge of
76
8
72
according to the timings in Table 2-18.
75
1, 2
Minimum
(1.5 × T
(2.5 × T
(1.5 × T
(2.5 × T
Expression
0.5
0.5
0.5
6
9
T
C
—
+ 5.0
C
C
C
C
) + 5.0
) + 5.0
) + 5.0
) + 5.0
Freescale Semiconductor
73
Maximum
—
—
—
—
9
Note 11
Note 11
Note 11
Note 11
Note 11
Value
5.0
Units
DLLIN
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.