MSC8103 Freescale Semiconductor / Motorola, MSC8103 Datasheet - Page 9

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MSC8103

Manufacturer Part Number
MSC8103
Description
Network Digital Signal Processor
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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1.3 Reset, Configuration, and EOnCE Event Signals
Freescale Semiconductor
DBREQ
EE0
HPE
EE1
EE2
EE3
CLKOUT
DLLIN
Signal Name
Signal Name
1
1
1
1
Output
Input
Output
Output
Output
Output
Type
Type
Input
Input
Input
Input
Input
Input
Table 1-4.
MSC8103 Network Digital Signal Processor, Rev. 12
Debug Request
Determines whether to go into SC140 Debug mode when PORESET is deasserted.
Enhanced OnCE (EOnCE) Event 0
After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
Debug request, enable Address Event Detection Channel 0, or generate an EOnCE event.
Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment.
Host Port Enable
When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits
wide, and the Host must program the reset configuration word.
EOnCE Event 1
After PORESET is deasserted, you can configure EE1 as an input (default) or an output.
Enable Address Event Detection Channel 1 or generate an EOnCE event.
Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external
debugging equipment.
EOnCE Event 2
After PORESET is deasserted, you can configure EE2 as an input (default) or an output.
Enable Address Event Detection Channel 2 or generate an EOnCE event or enable the Event
Counter.
Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment.
EOnCE Event 3
After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the
emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ERCV
Register.
Enable Address Event Detection Channel 3 or generate one of the EOnCE events.
The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment.
Clock Out
The system bus clock.
DLLIN
Synchronizes with an external device.
Note:
Table 1-3.
Reset, Configuration, and EOnCE Event Signals
When the DLL is disabled, connect this signal to GND.
Clock Signals (Continued)
Signal Description
Signal Description
Reset, Configuration, and EOnCE Event Signals
1-5

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