MSC8113 Freescale Semiconductor / Motorola, MSC8113 Datasheet - Page 36

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MSC8113

Manufacturer Part Number
MSC8113
Description
Tri-Core Digital Signal Processor
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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2.5.12
Figure 27 shows the signal behavior of the
2.5.13
36
Note:
Notes:
No.
700
701
702
703
704
705
706
707
708
709
710
711
712
713
Number
65
66
TCK frequency of operation (1/(T
TCK cycle time
TCK clock pulse width measured at V
TCK rise and fall times
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
1.
2.
High
Low
EE Signals
JTAG Signals
The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
EE0 (input)
EE1 (output)
Characteristics
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0
EE1 out
EE0 in
C
× 4); maximum 25 MHz)
M
EE
= 1.6 V
Characteristics
pins.
Figure 27. EE Pin Timing
Table 29. EE Pin Timing
Table 30. JTAG Timing
Synchronous to Core clock
Asynchronous
Type
65
66
4 core clock periods
1 core clock period
Freescale Semiconductor
100.0
Min
40.0
20.0
16.0
20.0
20.0
30.0
frequencies
0.0
0.0
5.0
0.0
0.0
5.0
0.0
0.0
Min
All
Max
30.0
30.0
20.0
20.0
3.0
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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