MSC8126 Freescale Semiconductor / Motorola, MSC8126 Datasheet - Page 41

• Manufacturer Part Number: MSC8126
• Description: Quad Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

Each
GND
chip. The
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip
be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as
GND
All output pins on the MSC8126 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
V
Figure 34. For optimal noise filtering, place the circuit as close as possible to
to
kept short and direct. Provide an extremely low impedance path to the ground plane for
by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
Freescale Semiconductor
Voltage Regulator
CCSYN
Power supply
V
(I
min
CCSYN
•
V
pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
planes.
or
= 3 A)
CC
-
GND
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8126 device.
V
and
, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to
CC
SYN
V
power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the
DD
. To ensure internal clock stability, filter the power to the
pin on the MSC8126 device should have a low-impedance path to the board power supply. Similarly, each
+
-
1.2 V
V
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
CC
V
,
DD
V
DD
Note: Use at least three capacitors.
Each capacitor must be at least 150 μF.
Figure 33. Core Power Supply Decoupling
, and
10Ω
Maximum IR drop
of 15 mV at 1 A
GND
Bulk/Tantalum capacitors
with low ESR and ESL
Figure 34. V
10nH
circuits. Pull up all unused inputs or signals that will be inputs during reset.
10 µF
CCSYN
Bypass
V
CCSYN
V
L
CCSYN
max
0.01 µF
input with a circuit similar to the one in
= 2 cm
V
. The 0.01-µF capacitor should be closest
CCSYN
GND
Hardware Design Considerations
SYN
High frequency capacitors
One 0.01 µF capacitor
for every 3 core supply
(very low ESR and ESL)
pads.
V
. Bypass
DD
V
CC
. These traces should be
,
V
DD
GND
, and
SYN
GND
MSC8122
to
V
V
CC
should
CCSYN
and
41