CS61310 Cirrus Logic, Inc., CS61310 Datasheet - Page 3

• Manufacturer Part Number: CS61310
• Description: Long Haul T1 Line Interface Unit
• Manufacturer: Cirrus Logic, Inc.

LIST OF FIGURES
LIST OF TABLES
DS440PP2
Table 1. Pulse Shape Selection and Transformer Requirements ...................................... 8
Table 2. Data Output/Clock Relationship ........................................................................... 9
Table 3. Register Map...................................................................................................... 12
Table 4. Register 16 Decoding......................................................................................... 15
Table 5. CS61310 Diagnostic Mode Availability .............................................................. 17
Table 6. Transformer Specification .................................................................................. 18
Table 7. Recommended Tranformers for the CS61310 ................................................... 18
Figure 1. Signal Rise and Fall Characteristics ................................................................. 6
Figure 2. Recovered Clock and Data Switching Characteristics ...................................... 6
Figure 3. Transmit Clock and Data Switching Characteristics ......................................... 6
Figure 4. Serial Port Write Timing Diagram ..................................................................... 7
Figure 5. Serial Port Read Timing Diagram ..................................................................... 7
Figure 6. Typical Pulse Shape for DS-1 ........................................................................... 8
Figure 7. Minimum Input Jitter Tolerance of Receiver ................................................... 10
Figure 8. LATN Pulse Width encoding ........................................................................... 10
Figure 9. Typical Jitter Transfer Function ....................................................................... 10
Figure 10. Input/Output Timing (showing address 0x10) ............................................... 12
Figure 11. Phase Definition of Arbitrary Waveforms ...................................................... 16
Figure 12. Example of Summing of Waveforms ............................................................. 17
Figure 13. Hardware Mode Operation ............................................................................ 26
Figure 14. Matched Impedence Output Configuration ................................................... 27
Figure 15. Typical System Connection .......................................................................... 28
CS61310
3