STE2007 STMicroelectronics, STE2007 Datasheet - Page 20

• Manufacturer Part Number: STE2007
• Description: 96 x 68 Single Chip LCD Controller/Driver
• Manufacturer: STMicroelectronics

4 INTERFACE
Figure 10. 4-lines SPI Commands Transfe
Figure 11. 4-lines SPI Video Data Write Cycle
4.2.1.1 Data/Command Transfer break
4.2.1.2 Data/Command Transfer pause
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(output)
(output)
(input)
(input)
SDA
SDA
SDA
SDA
D/!C
D/!C
SCL
SCL
!CS
!CS
Hi-Z
Hi-Z
If the Host processor generates an break condition (!CS Line HIGH before having received Bit
D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command
parameter, the not complete received byte is discarded, the communication is interrupted and
the interface is forced in reset state.
When !CS line becomes low again to start a new communication session STE2007 is ready to
receive the same byte interrupted re-transmitted or a new command identifier.
Figure 12. 4-lines SPI Data Transfer break condition
It is possible while transferring Frame Memory Data, Commands or Command Parameters to
insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is
forced high after a whole byte received, the received byte is processed. Then STE2007 is
forced in a wait state ready to restart processing incoming data from the point where the
communication has been paused
D7
D7
D6
D6
D5
D5
COMMAND
COMMAND
D4
D4
D3
D3
D/!C
!CS
SCL
SDA
D2
D2
D1
D1
D0
D0
D7
D7
D6
D6
D7
D5
D5
DATA to VIDEO RAM
COMMAND/PARAMETER
COMMAND
D4
D4
D6
D3
D3
D2
D2
D1
D1
D5
D0
D0
D7
D7
D4
D6
D6
DATA to VIDEO RAM
D5
D5
D3
COMMAND
D4
D4
D3
D3
Break
D2
D2
D1
D1
D0
D0
D7
D7
D7
D6
D6
COMMAND/PARAMETER
D6
D5
D0
D0
D7
D7
D6
D6
D4
D5
D5
DATA to VIDEO RAM
COMMAND
D4
D4
D3
LR0192
D3
D3
D2
D2
STE2007
D1
D1
LR0189
LR0190
D0
D0