STE2007 STMicroelectronics, STE2007 Datasheet - Page 23

• Manufacturer Part Number: STE2007
• Description: 96 x 68 Single Chip LCD Controller/Driver
• Manufacturer: STMicroelectronics

STE2007
4.3.1
4.3.2
Figure 15. Bit transfer and START,STOP conditions definition
Figure 16. Acknowledgment on the I
Communication Protocol
The STE2007 is an I
status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits
(01111). The two least significant bit of the slave address are set by connecting the SA0 and
SA1 inputs to a logic 0 or to a logic 1.
Starting the Communication
To start the communication between the bus master and the slave LCD driver, the master must
initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line
(Most significant bit first). This consists of the 7-bit Device Address Code, and the 1-bit Read/
Write Designator (R/W). The R/W bit has to be set to logic 1 to logic 0 according to the type of
communication (read or write).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the
I
2
C-bus transfer.
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
SCLK FROM
MASTER
CLOCK
DATA
CONDITION
START
START
2
C slave. The access to the device is bi-directional since data write and
MSB
1
ADDRESS BYTE
DATA VALID
DATA LINE
STABLE
2
C-bus
DATA ALLOWED
CHANGE OF
SLAVE ADDRESS
2
0 1 1 1 1
STE2007
D00IN1152
READ or WRITE
DESIGNATOR
S
A
1
S
A
0
W
R
D00IN1151
/
8
LSB
CONDITION
STOP
ACKNOWLEDGEMENT
CLOCK PULSE FOR
4 INTERFACE
9
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