STE2004DIE1 STMicroelectronics, STE2004DIE1 Datasheet - Page 28

• Manufacturer Part Number: STE2004DIE1
• Description: 102 x 65 SINGLE CHIP LCD CONTROLLER / DRIVER
• Manufacturer: STMicroelectronics

STE2004
4.1.2 Writing Mode.
If the R/W bit is set to logic 0 the STE2004 is set to be a receiver. After the slaves acknowledge one or
more command word follows to define the status of the device.
A command word is composed by three bytes. The first is a control byte which defines the Co and D/C
values, the second and third are data bytes. The Co bit is the command MSB and defines if after this com-
mand will follow two data bytes and an other command word or if will follow a stream of data (Co = 1 Com-
mand word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data
(D/C = 1 RAM Data, D/C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the
following data byte will be stored in the data RAM at the location specified by the data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2004
Display RAM starting at the address specified by the data pointer. The data pointer is automatically up-
dated after every byte written and in the end points to the last RAM location written.
Every byte must be acknowledged by all addressed units.
4.1.3 Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit
during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 33. Communication Protocol
4.2 SERIAL INTERFACES
STE2004 can feature three different serial synchronized interfaces with the host controller. It is possible to select
a 3-lines SPI, a 4-lines SPI or 3-line 9 bits Serial Interface.
4.2.1 4-lines SPI interface
STE2004 4-lines serial interface is a bidirectional link between the display driver and the application supervisor.
It consists of four lines: one/two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the pe-
ripheral enable (CS) and one for mode selection (SD/C).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power
consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-
ter.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C line is read on
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WRITE MODE
S
S
READ MODE
SLAVE ADDRESS
0 1 1 1 1
0 1 1 1 1
S
A
1
S
A
1
DRIVER ACK
DRIVER ACK
S
A 0 A
S
A 1 A
0
0
R/W
R/W
Co
1 DC Control Byte
COMMAND WORD
MASTER ACK
DRIVER ACK
A
P
DATA Byte
SLAVE ADDRESS
0 1 1 1 1
DRIVER ACK
DRIVER
A 0
Co
CONTROL BYTE
DC Control Byte
S
A
1
S
A
0
LAST
W
R
/
DRIVER ACK
A
C
o
D
C
CONTROL BYTE
MSB........LSB
0 0 0
N> 0 BYTE
DATA Byte
H
E
[1]
H
DRIVER ACK
[0]
H
LR0008
A
A P