FPD750SOT343CE Filtronic, FPD750SOT343CE Datasheet - Page 2

• Manufacturer Part Number: FPD750SOT343CE
• Description: LOW NOISE HIGH LINEARITY PACKAGED PHEMT
• Manufacturer: Filtronic

A
Notes:
1
permanent damage to the device
2
3
4
B
•
•
•
Total Power Dissipation to be de-rated as follows above 22°C:
T
Max. RF Input Limit must be further limited if input VSWR > 2.5:1
Users should avoid exceeding 80% of 2 or more Limits simultaneously
Total Power Dissipation defined as: P
Simultaneous Combination of Limits
BSOLUTE
Ambient
IASING
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Channel Operating Temperature
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices.
For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Class A/B
bias of 25-33% offers an optimised solution for NF and OIP3.
Total Power Dissipation
0.0
Drain-Source Voltage
Drain-Source Current
Storage Temperature
Gate-Source Voltage
= 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
Gain Compression
P
where P
P
where T
RF Input Power
TOT
ARAMETER
Gate Current
G
0.5
UIDELINES
= 1.1 - (1/Θjc) x T
M
1.0
AXIMUM
PACK
DC
1.5
: DC Bias Power, P
2
= source tab lead temperature above 22°C & Θjc = 143ºC/W
4
2.0
Drain-Source Voltage (V)
:
R
DC IV Curves FPD750SOT89
3
2.5
ATING
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PACK
3.0
1
Specifications subject to change without notice
3.5
:
S
Filtronic Compound Semiconductors Ltd
YMBOL
TOT
Comp.
TSTG
PTOT
IN
VDS
VGS
TCH
IDS
PIN
IG
4.0
: RF Input Power, P
≡ (P
4.5
DC
5.0
+ P
IN
5.5
) – P
Under any acceptable bias state
2
Forward or reverse current
See De-Rating Note below
6.0
T
Under any bias conditions
Non-Operating Storage
OUT
EST
2 or more Max. Limits
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-3V < VGS < -0.5V
OUT
VG=-1.50
VG=-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.50V
VG=-0.25V
VG=0V
0V < VDS < +6V
For VDS < 2V
,
VDS = 3.3V
C
: RF Output Power
ONDITIONS
Note:
measuring I
the Drain-Source voltage (V
measurement point avoids the onset of
spurious self-oscillation which would normally
distort the current measurement (this effect has
been filtered from the I-V curves presented
above). Setting the V
cause errors in the current measurements,
even in stabilized circuits.
FPD750SOT343
The
DSS
, or any particular I
Website:
A
recommended
BSOLUTE
-55°C to 150°C
DS
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22dBm
7.5mA
175°C
1.1W
> 1.3V will generally
IDss
80%
5dB
-3V
6V
M
DS
AXIMUM
) at 1.3V. This
Datasheet v3.0
method
DS
, is to set
for