FPD87392BXB National Semiconductor, FPD87392BXB Datasheet

no-image

FPD87392BXB

Manufacturer Part Number
FPD87392BXB
Description
+3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)
Manufacturer
National Semiconductor
Datasheet
© 2004 National Semiconductor Corporation
FPD87392BXB
+3.3V TFT-LCD Timing Controller with Dual LVDS
Inputs/Dual RSDS
Notebook (SXGA/SXGA+/UXGA)
General Description
The FPD87392BXB Panel Timing Controller is an integrated
FPD-Link + RSDS
architecture is implemented using standard and default tim-
ing controller functionality based on an Embedded Gate
Array. The device is reconfigurable to the needs of a specific
application by providing user-defined specifications or cus-
tomer supplied VHDL/Verilog code.
The FPD87392BXB is a timing controller that combines an
LVDS dual pixel input interface with National’s Reduced
Swing Differential Signaling (RSDS
interface for SXGA, SXGA+ and UXGA resolutions. It re-
sides on the TFT-LCD panel and provides the data buffering
and control signal generation. The RSDS
column driver contributes toward lowering radiated EMI and
reduced system dynamic power consumption. The RSDS
dual 12 pair differential bus conveys up to 24-bit color data
for SXGA/SXGA+/UXGA panels when using VESA 60Hz
standard timing.
+ TFT-LCD Timing Controller. The logic
) output column driver
DS201043
Outputs for TFT-LCD Monitor and
data path to the
Features
n Input frequency range from 25 MHz to 85 MHz
n Support display resolutions SXGA (1280x1024), SXGA+
n Embedded gate array for custom panel timing
n RSDS
n Drives RSDS
n 6 or 8 bit LVDS dual pixel input interface (FPD-Link)
n Virtual 8-bit color depth in FRC mode
n Flexible RSDS
n Supports 1 and 2 line inversion mode for RVS output
n Supports Graphics Controllers with spread spectrum
n Free Run Mode Function
n Fail-safe function in DE mode (Bonding Option)
n Supports DE mode and SYNC only mode (Bonding
n Power-On-Reset Support
n CMOS circuitry operates from a 3.0V to 3.6V supply
n 128 TQFP package with body size 14mm x 14mm x
(1400x1050) and UXGA (1600x1200)
Driver bus for low power and reduced EMI
MHz clock
mount
interface for lower EMI
Option)
1.0mm, 0.4mm Pitch
(Reduced Swing Differential Signaling) Column
column driver up to 170 Mb/s with an 85
data output mapping for Bottom or Top
www.national.com
July 2004

Related parts for FPD87392BXB

FPD87392BXB Summary of contents

Page 1

... Embedded Gate Array. The device is reconfigurable to the needs of a specific application by providing user-defined specifications or cus- tomer supplied VHDL/Verilog code. The FPD87392BXB is a timing controller that combines an LVDS dual pixel input interface with National’s Reduced Swing Differential Signaling (RSDS ™ ...

Page 2

System Diagram www.national.com FIGURE 1. Block Diagram of the LCD Module 2 20104301 ...

Page 3

Block Diagram Functional Description DUAL FPD-LINK RECEIVERS The LVDS based FPD-Link Receivers inputs video data and control timing through 8 pairs of LVDS channels plus 2 pairs of LVDS clocks to provide 24-bit color or use only 6 pairs of ...

Page 4

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( TTL Input Voltage ( LVDS Input Voltage ( Output Voltage (V ) OUT Junction Temperature Storage Temperature Range (T ) STG Lead Temperature (T ...

Page 5

DC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V FPD-Link (LVDS) Receiver Input Characteristics Symbol Parameter LVDS RECEIVER DC SPECIFICATIONS Note: LVDS Receiver DC parameters are measured under static and steady state conditions ...

Page 6

DC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V RSDS Output Symbol Parameter V Differential Output Voltage OD RSDS V Offset Voltage OS RSDS FIGURE 6. RSDS Output Waveforms: Single Ended vs Differential ...

Page 7

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V LVDS Data Input Symbol RPLLS FPD-Link Receiver Phase Lock Loop Wake-up Time RSKM RxIN Skew Margin (Note 2) and (Figure 7) Note 2: Receiver ...

Page 8

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V FIGURE 9. FPD-Link ReceiverSS Input Data Mappings (Default) FIGURE 10. FPD-Link Receiver NS Input Data Mappings www.national.com = 100 µA (Unless otherwise specified) (Continued) ...

Page 9

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V FIGURE 11. FPD-Link Receiver Phase Lock Loop Wake-up Time = 100 µA (Unless otherwise specified) (Continued 20104309 www.national.com ...

Page 10

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V Output Timing Symbol Parameter RCHP RSDS Clock (RSCK) High Period RCLP RSDS Clock (RSCK) Low Period SPSTU STH Rising to RSCK Falling SPHLD STH ...

Page 11

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V FIGURE 12. RSDS and TTL (CMOS) Output Timing Diagram = 100 µA (Unless otherwise specified) (Continued 20104310 20104311 www.national.com ...

Page 12

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V www.national.com = 100 µA (Unless otherwise specified) (Continued) PI FIGURE 13. RSDS Output Data Mapping 12 20104312 ...

Page 13

AC Electrical Characteristics T = 0˚C to 70˚ 3.0V to 3.6V Failure Detect (B/O pin “FDE” = High) This function is valid in DE mode and FDE pin set to “High”. Invalid external DE pulse ...

Page 14

Output Timing—TTL Comments Parameter (TPW, OE2, OE1 : 3’b000) t1 STH Rising to Active Data t2 High Duration of STH t3 STH Rising to TP Rising t4 High Duration STH Rising to OE Falling t6 High Duration ...

Page 15

Output Timing—TTL (Continued) FIGURE 14. TTL Output Timing Diagram 15 20104314 www.national.com ...

Page 16

Output Timing—TTL FIGURE 15. Typical TTL Output Timing Diagram (continued) www.national.com (Continued) 16 20104315 ...

Page 17

Output Timing—TTL (Continued) FIGURE 16. TTL Output Timing with Blanking 17 20104316 www.national.com ...

Page 18

Output Timing—TTL 8–BIT RSDS Output Data Mapping DMAP2, DMAP1 Pin 00 01 No. Top Mount 47 R3P_F R0N_F B0N_B 48 R3N_F R0P_F B0P_B 49 R2P_F R1N_F B1N_B 50 R2N_F R1P_F B1P_B 51 R1P_F R2N_F B2N_B 52 R1N_F R2P_F B2P_B 53 ...

Page 19

Output Timing—TTL 6–BIT RSDS Output Data Mapping DMAP2, DMAP1 Pin No Top Mount 47 HI-Z R0N_F 48 HI-Z R0P_F 49 R2P_F R1N_F 50 R2N_F R1P_F 51 R1P_F R2N_F 52 R1N_F R2P_F 53 R0P_F HI-Z 54 R0N_F HI-Z 56 ...

Page 20

Input Signal Timing Sync only mode inputted, is supported when the SYNC pin (Bonding Option pin) is enable high. Whenever DE signal is inputted, it works as DE mode. In the DE mode, H-blank min is considered with ...

Page 21

Power Up Sequence (Defaults) When Power is ON, the TCON start to operate and generate the control signals by inputted LVDS signals. LVDS Receiver will take maximum 10 ms for the PLL wake-up time. Whether LVDS signals exist before the ...

Page 22

Pin Connection www.national.com 22 20104319 ...

Page 23

Pin Connection (Continued) 23 20104320 www.national.com ...

Page 24

Pin Connection (Continued) www.national.com 24 20104321 ...

Page 25

Pin Connection (Continued) 25 20104322 www.national.com ...

Page 26

Pin Description System Interface Symbol Pin No. RxINO[0]P/N and 4, 5 RxINE[0]P/N 19, 20 RxINO[1]P/N and 6, 7 RxINE[1]P/N 21, 22 RxINO[2]P/N and 8, 9 RxINE[2]P/N 23, 24 RxINO[3]P/N and 12, 13 RxINE[3]P/N 25, 26 RxCLKOP/N and 10, 11 RxCLKEP/N ...

Page 27

Pin Description (Continued) Control Input Symbol Pin No. BIT_CFG1/2 37, 38 MODE[1:0] 122, 33 DMAP1/2 39, 40 TPW 125 OEW1/2 126, 127 TEST1/2 128, 1 PDI 32 RSTB 34 RxMap 120 NC 111, 116 Power Supply Symbol Pin No. V ...

Page 28

Appendix 1. DE Mode Timing Details DE Mode (Disabled SYNC Pin) Always true whenever DE is exist as inputted signal the control timing. “V-blank Detection” period is two cycles of the previous DE signals. After the V-blank detection ...

Page 29

Appendix 3. Power-Up Sequence on “POR Enabled” Mode When Bonding option pins, POR (Power-On-Reset), enable set to “High”, TCON start running as POR mode. If the input LVDS clocks lost with any reasons during the normal operation, POR output signal ...

Page 30

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted 128–lead Plastic Quad Flatpack, JEDEC Dimensions in millimeters only Order Number FPD87392BXBVQ NS Package Number VJX128A 2. A critical component is any component of a life support device or system whose failure to perform ...

Related keywords