FPD87392BXB National Semiconductor, FPD87392BXB Datasheet - Page 7

• Manufacturer Part Number: FPD87392BXB
• Description: +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)
• Manufacturer: National Semiconductor

RPLLS
RSKM
AC Electrical Characteristics
T
LVDS Data Input
Note 2: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window: RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type and length of cable), and source clock (FPD-Link Transmitter TxCLK IN) jitter. The specified RSKM minimum assumes a
TPPOS max of 200 ps.
RSKM = cable skew (type, length) + source clock jitter (cycle to cycle) + remaining margin for data sampling (≥0)
This parameter is guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (Process, Voltage, Temperature) range.
Acronyms:
RSKM
TPPOS
RSPOS
SW
Definitions:
SW:
RSKM:
Cable Skew: Typically 10 ps − 40 ps per foot.
A
= 0˚C to 70˚C, V
Symbol
Receiver Skew Margin
Setup and Hold Time (Internal data sampling window)
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + Remaining margin for data sampling (≥ 0)
Transmitter Pulse Position
Receiver Strobe Position
Strobe Width
DD
FPD-Link Receiver Phase Lock Loop Wake-up Time
RxIN Skew Margin (Note 2) and (Figure 7)
= 3.0V to 3.6V, I
FIGURE 7. FPD-Link Receiver Input Skew Margin
FIGURE 8. Ideal Strobe Position for LVDS Input
PI
= 100 µA (Unless otherwise specified)
Parameter
7
V
CLK = 85 MHz
DD
Conditions
= 3.3V,
20104307
20104306
Min
240
Max
10
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Units
ms
ps