S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 381
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S1D13705
Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13705.pdf
(480 pages)
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Vancouver Design Center
3.2 Generic #2 Interface Mode
Interfacing to the PC Card Bus
Issue Date: 01/02/13
Generic #2 interface mode is a general and non-processor-specific interface mode on the
S1D13705. The Generic # 2 interface mode was chosen for this interface due to the
simplicity of its timing and compatibility with the PC Card bus control signals.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
• WE1# is the high byte enable for both read and write cycles.
• WE0# is the write enable for the S1D13705, to be driven low when the host CPU is
• RD# is the read enable for the S1D13705, to be driven low when the host CPU is
• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
S1D13705. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock.
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
register and memory address space.
writing data to the S1D13705.
reading data from the S1D13705.
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the S1D13705 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 13705 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
face for Generic #2 mode. However, BS# is used to configure the S1D13705 for
Generic #2 mode and should be tied high (connected to IO V
be tied high.
DD
). RD/WR# should also
X27A-G-009-02
S1D13705
Page 11
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