S1M8831A Samsung Semiconductor, Inc., S1M8831A Datasheet - Page 14

• Manufacturer Part Number: S1M8831A
• Description: Fractional-n Rf/integer-n If Dual Pll Frequency Synthesizer
• Manufacturer: Samsung Semiconductor, Inc.

S1M8831A/33
The RF part of S1M8831A/33 adopts the
to obtain divide ratio N to be a fractional number between two contiguous integers. The
randomizes the quantization noise generated from digitizing process and results in extreme suppression of in-
band noise power by pushing it out to out-of-band as in conventional
eliminates the need for compensation current injection into the loop filter and improves fractional spurious
performance, suitable for high-tier applications.
The - modulator operates only for fractional-N mode, when the Frac-N_SEL is HIGH.
For proper use of the fractional mode, the user should be kept in mind that
1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976.
2. The clock frequency fixed at 9.84MHz ( = 19.68MHz/2) is recommended for the - modulator which is an
Phase-Frequency Detector (PFD) and Charge Pump (CP)
The RF/IF phase detector composed of PFD and CP outputs pump current into an external loop filter in
proportional to the phase difference between outputs of N and R counter . The phase detector has a better linear
transfer characteristic due to a feedback loop to eliminate dead zone. The polarity of the PFD can be
programmed using RF_PFD_POL/IF_PFD_POL depending on whether RF/IF VCO characteristics are positive or
negative. (programming descriptions for phase detector polarity)
Power-Down (or Power-Save) Control
Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits
(PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the
program control bits determine the state of power control. Power down forces all the internal blocks to be
deactivated and the charge pump output to be in the TRISTATE. The control register, however, remains active
for serial programming and is capable of loading and latching in data during the power down.
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optimum condition for achieving better electrical performances related to the fractional noise and power
consumption. Only when using the clock frequency, the S1M8831A/33 guarantees the exact frequency
resolutions: 10kHz for CDMA PCS and 30kHz for CDMA cellular.
Note that the clock frequency much lower than 9.84MHz can deteriorate the fractional noise performance.
Modulator
- modulator as a core of the fractional counter that makes it possible
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
- data converter. This technique
- modulator effectively