XA-G3 NXP Semiconductors, XA-G3 Datasheet

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XA-G3

Manufacturer Part Number
XA-G3
Description
Xa 16-bit Microcontroller Family 32k/512 Otp/rom/romless, Watchdog, 2 Uarts
Manufacturer
NXP Semiconductors
Datasheet
Philips
Semiconductors
Product specification
Supersedes data of 1998 Aug 14
IC25 Data Handbook
XA-G3
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
INTEGRATED CIRCUITS
1999 Apr 07

Related parts for XA-G3

XA-G3 Summary of contents

Page 1

... XA-G3 XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs Product specification Supersedes data of 1998 Aug 14 IC25 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1999 Apr 07 ...

Page 2

... Low power operation, which is intrinsic to the XA architecture, includes power-down and idle modes. More detailed information on the core is available in the XA User Guide. SPECIFIC FEATURES OF THE XA-G3 20-bit address range, 1 megabyte each program and data space. (Note that the XA architecture supports bit addresses.) 2.7V to 5.5V operation ...

Page 3

... SU00525 XTAL1 XTAL2 RST EA/WAIT PSEN ALE 3 Product specification XA- LQFP Function Pin Function P1.5/TxD1 23 P2.5/A17D13 P1.6/T2 24 P2.6/A18D14 P1.7/T2EX 25 P2.7/A19D15 RST 26 PSEN P3.0/RxD0 27 ALE/PROG P3.1/TxD0 29 EA/V /WAIT PP P3.2/INT0 30 P0 ...

Page 4

... XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs BLOCK DIAGRAM 32K BYTES ROM/EPROM 512 BYTES STATIC RAM PORT 0 PORT 1 PORT 2 PORT 3 1999 Apr 07 XA CPU Core Program SFR BUS Memory Bus Data Bus 4 Product specification XA-G3 UART0 UART1 TIMER 0 & TIMER 1 TIMER 2 WATCHDOG TIMER SU00527 ...

Page 5

... Timer 1 external input, or timer 1 overflow output. The value on this pin is latched as the external reset input is released and defines the default external data bus width (BUSW 8-bit bus and 1 = 16-bit bus. WRL (P3.6): External data memory low byte write strobe. RD (P3.7): External data memory read strobe. 5 Product specification XA-G3 ...

Page 6

... AD7 AD6 AD5 AD4 38F 38E 38D 38C 431 T2EX T2 TxD1 RxD1 397 396 395 394 432 P2.7 P2.6 P2.5 P2.4 6 Product specification XA-G3 RESET VALUE LSB BUSD BC2 BC1 BC0 Note 1 DR1 DR0 DRA1 DRA0 FF CR1 CR0 CRA1 CRA0 33B 33A 339 ...

Page 7

... ESWEN R6SEG R5SEG R4SEG 47A — SWE7 SWE6 SWE5 7 Product specification XA-G3 RESET RESET VALUE VALUE LSB 39B 39A 399 398 INT1 INT0 TxD0 RxD0 FF Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ...

Page 8

... The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The XA-G3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide . All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte. ...

Page 9

... Philips Semiconductors XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs XA-G3 TIMER/COUNTERS The XA has two standard 16-bit enhanced Timer/Counters: Timer 0 and Timer 1. Additionally, it has a third 16-bit Up/Down timer/counter, T2. A central timing generator in the XA core provides the time-base for all XA Timers and Counters. The timer/event counters can perform the following functions: – ...

Page 10

... When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not requiring an interrupt. TR1 TF0 TR0 IE1 IT1 10 Product specification XA-G3 LSB IE0 IT0 SU00604C ...

Page 11

... TL2 and TH2, respectively. A logic ‘0’ at pin T2EX causes Timer 2 to count down. When counting down, the timer value is compared to the 16-bit value contained in T2CAPH and T2CAPL. When the value is equal, the 11 Product specification XA-G3 LSB C/T2 CP/RL2 SU00606A ...

Page 12

... T2EX pin X X — — — — T1OE — RCLK1 TCLK1 — — Figure 6. Timer 2 Mode Control (T2MOD) 12 Product specification XA-G3 TCLK MODE Timer off (stopped) 16-bit capture Baud rate generator LSB — T0OE SU00612B LSB T2OE DCEN SU00610B ...

Page 13

... T2CAPL T2CAPH Control (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 T2CAPL T2CAPH (UP COUNTING RELOAD VALUE) Figure 9. Timer 2 Auto Reload Mode (DCEN = 1) 13 Product specification XA-G3 TF2 Timer 2 Interrupt EXF2 SU00704 TF2 Timer 2 Interrupt EXF2 SU00705 TOGGLE EXF2 TF2 INTERRUPT COUNT ...

Page 14

... When coming out of a hardware reset, the software should load the autoload register and then feed the watchdog (cause an autoload). If the watchdog is running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be cleared. 14 Product specification XA-G3 4096 t and the OSC PRE0 DIVISOR ...

Page 15

... WDTOF Timeout flag WDCON.0 — UARTs The XA-G3 includes 2 UART ports that are compatible with the enhanced UART used on the 8xC51FB. Baud rate selection is somewhat different due to the clocking scheme used for the XA timers. Some other enhancements have been made to UART operation. ...

Page 16

... TI_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the EA bit in the IEL register. Note Regarding Older XA-G3 Devices Older versions of the XA-G30, XA-G37, and XA-G35 emulation bondout devices do not have the double buffering feature enabled. Contact factory for details. 16 ...

Page 17

... T2CON 0x418 T2MOD 0x419 Prescaler Select for Timer Clock (TCLK) SCR 0x440 — — — — FEn (See also Figure 13 regarding Framing Error flag) 17 Product specification XA-G3 bit5 bit4 RCLK0 TCLK0 bit5 bit4 RCLK1 TCLK1 bit3 bit2 PT1 PT0 LSB BRn OEn ...

Page 18

... Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature. 18 Product specification XA-G3 1100 0000 1111 1101 = 1100 00X0 1100 0000 ...

Page 19

... FEn BRn Figure 13. UART Framing Error Detection SM0_n SM1_n SM2_n REN_n COMPARATOR 19 Product specification XA-G3 LSB TB8 RB8 TI RI SU00597C ONLY IN STOP MODE 2, 3 BIT if 0, sets FE SnSTAT OEn STINTn SU00598 D7 D8 SnCON TB8_n ...

Page 20

... POWER REDUCTION MODES The XA-G3 supports Idle and Power Down modes of power reduction. The idle mode leaves some peripherals running to allow them to wake up the processor when an interrupt is generated. The power down mode stops the oscillator in order to minimize power. ...

Page 21

... IEL or IEH registers). Only three bits of the IPA register values are used on the XA-G3. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5. The value 0 in the IPA field gives the interrupt priority 0, in effect disabling the interrupt ...

Page 22

... 1mA 2. 0.45V 5.5V must be externally limited as follows 5V.) DD vs. Frequency Product specification XA-G3 RATING UNIT –55 to +125 C –65 to +150 +13.0 V –0 +0. 1.5 W LIMITS UNIT UNIT MIN TYP MAX ...

Page 23

... WAIT hold after bus strobe (RD, WR, or PSEN) assertion WTL NOTES ON PAGE 24. 1999 Apr 07 PARAMETER PARAMETER ( ( ( ( ( (V12 * t (V13 * t (V11 * t ( (V11 * t (V10 * t 23 Product specification XA-G3 VARIABLE CLOCK UNIT UNIT MIN MAX 0 30 MHz ...

Page 24

... CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If CRA1 and ALEW = 1, the – (1 1999 Apr 07 PARAMETER PARAMETER ( ( ( ( ( (V12 * t (V13 * t (V11 * t ( (V11 * t (V10 * t 24 Product specification XA-G3 VARIABLE CLOCK UNIT UNIT MIN MAX – – /2) – – ...

Page 25

... This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case, and in most applications this parameter is not used. 6. Please note that the XA-G3 requires that extended data bus hold time (WM0 = used with external bus write cycles. 1999 Apr 07 ...

Page 26

... Figure 17. External Program Memory Read Cycle (Non-ALE Cycle) 1999 Apr 07 t LLPL t PLPH t PLIV t LLAX t PXIZ t PLAZ t PXIX * INSTR IN t IXUA t AVIVA A0 or A1–A3, A12–19 * INSTR A1–A3, A12–19 26 Product specification XA-G3 SU00946 t AVIVB A0 or A1–A3, A12–19 SU00707 ...

Page 27

... Figure 19. External Data Memory Read Cycle (Non-ALE Cycle) 8 Bit Bus Only 1999 Apr LLRL RLRH t RHDZ t RLDV t RHDX * DATA AVDVA A0 or A1–A3, A12–A19 D0–D7 A0–A3, A12–A19 27 Product specification XA-G3 DXUA SU00947 * DATA IN t AVDVB A0–A3, A12–A19 SU00708A ...

Page 28

... RD, OR PSEN) t WTH 1999 Apr WLWH LLWL t QVWX * DATA OUT A1–A3, A12–A19 Figure 20. External Data Memory Write Cycle t (The dashed line shows the strobe without WAIT.) WTL Figure 21. WAIT Signal Timing 28 Product specification XA-G3 t WHQX UAWH SU00584C SU00709A ...

Page 29

... DD Figure 23. AC Testing Input/Output +0.1V TIMING REFERENCE POINTS –0.1V /V level occurs Figure 24. Float Waveform (NC) CLOCK SIGNAL SU00591B Figure 26 Product specification XA-G3 SU00842 SU00703A V –0. +0. 20mA SU00011 RST EA XTAL2 ...

Page 30

... Apr FREQUENCY Figure 27. I vs. Frequency 5. FREQUENCY Figure 28. I vs. Frequency 3. Product specification XA-G3 MAX. I (ACTIVE) DD TYPICAL I (ACTIVE) DD MAX. I (IDLE) DD TYPICAL I (IDLE SU01192 MAX. I (ACTIVE) DD TYPICAL I (ACTIVE) DD MAX. I (IDLE) DD TYPICAL I (IDLE ...

Page 31

... DD t CHCX CHCL CLCX CLCH t CL Tests in Active and Idle Modes 5ns CLCH CHCL RST EA (NC) XTAL2 XTAL1 V SS SU00585A Test Condition, Power Down Mode DD All other pins are disconnected. V = Product specification XA-G3 SU00608A ...

Page 32

... Same as 3, external execution is disabled. Internal data RAM is not accessible. NOTES – programmed. U – unprogrammed. 2. Any other combination of the security bits is not defined. ROM CODE SUBMISSION When submitting ROM code for the XA-G33, the following must be specified: 1. 32k bytes user ROM data. 2. ROM security bits. ADDRESS CONTENT ...

Page 33

... Philips Semiconductors XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 1999 Apr 07 33 Product specification XA-G3 SOT389-1 ...

Page 34

... Philips Semiconductors XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs PLCC44: plastic leaded chip carrier; 44 leads 1999 Apr 07 34 Product specification XA-G3 SOT187-2 ...

Page 35

... Philips Semiconductors XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs 1999 Apr 07 NOTES 35 Product specification XA-G3 ...

Page 36

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 1999 Apr 07 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 36 Product specification XA-G3 All rights reserved. Printed in U.S.A. Date of release: 04-99 9397 750 05538 ...

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