CY39100V Cypress Semiconductor Corporation., CY39100V Datasheet - Page 36

• Manufacturer Part Number: CY39100V
• Description: Cplds At Fpga Densities
• Manufacturer: Cypress Semiconductor Corporation.

Switching Waveforms
Channel Memory Synchronous FIFO Master Reset Timing
Document #: 38-03039 Rev. *I
HALF-FULL/
PROGRAMMABLE
ALMOST FULL
FLAGS
EMPTY/FULL
PROGRAMMABLE
ALMOST EMPTY
FLAGS
MASTER
RESET INPUT
READ ENABLE /
WRITE ENABLE
REGISTERED
OUTPUT
Cypress Semiconductor ID
Family Type
39 = Delta39K Family
Gate Density
30=30k Usable Gates
50=50k Usable Gates
Operating Reference Voltage
Pin Count
208 = 208 Leads
256 = 256 Balls
388 = 388 Balls
V = 3.3V or 2.5V Supply Voltage
Z = 1.8V
Supply Voltage
484 = 484 Balls
676 = 676 Balls
100=100k Usable Gates
200=200k Usable Gates
(continued)
CY 39 050 V 208 - 125 NT X C
t
t
t
CHMFRSF
CHMFRSF
CHMFRSF
t
CHMFRS
t
CHMFRSR
Opearting Conditions
Commercial
Industrial
Lead Free
X
Package Type
A = Thin Quad Flat Pack (TQFP)
U = Ceramic Quad Flat Pack (CQFP)
N = Plastic Quad Flat Pack (PQFP)
NT = Thermally Enhanced Plastic Quad Flat
J = Plastic Leaded Chip Carrier (PLCC)
Y = Ceramic Leaded Chip Carier (CLCC)
BG = Plastic Ball Grid Array (PBGA)
BA = Fine-Pitch Ball Grid Array (FBGA)
BB = Fine-Pitch Ball Grid Array (FBGA)
Speed
100 = 100MHz
66 = 66MHz
83 = 83MHz
Pack (EQFP)
0.8mm Lead Pitch
1.0mm Lead Pitch
Lead (Pb) Free
Delta39K™ ISR™
-40
0
o
o
C to +70
C to +85
143 = 143MHz
154 = 154 MHz
167 = 167MHz
CPLD Family
o
o
C
C
Page 36 of 86
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