78Q2132 TDK Corp., 78Q2132 Datasheet - Page 20

• Manufacturer Part Number: 78Q2132
• Description: 1/10base-t Homepna/ethernet Transceiver
• Manufacturer: TDK Corp.

78Q2132
1/10BASE-TX
HomePNA/Ethernet Transceiver
REGISTER DESCRIPTION
P1R0-14 - Programmable Register Map, PAGE 1
REGISTER
0
1
2
SYMBOL
CONTROL
STATUS
IMASK (IMR)
TYPE
R/W
R/W
R/W
(continued)
DESCRIPTION
The CONTROL register provides a common location for
controlling the general operation of the PHY. This register
is composed of the following bit fields:
The STATUS register provides information regarding the
global aspects of the operation of the PHY. This register is
composed of the following bit fields:
The interrupt mask register determines which interrupt
sources may activate the INTR function. When low, the
interrupt is off. The various interrupt sources are mapped
into this register (as well as the ISTAT register) as follows:
bit 0 = (reserved)
bit 1 = high power
bit 2 = high speed
bit 4,3 = (reserved)
bit 5 = stop SLICE_LVL adaptation
bit 6 = clear the NSE_EVENTS register
bit 7 = stop AID address negotiation
bit 8 = Cmd high speed
bit 9 = Cmd low speed
bit 10 = Cmd high power
bit 11 = Cmd low power
bit 12-14 = (reserved)
bit 15 = ignore remote commands
bit 0-3 = (reserved)
bit 4 = RxVERSION
bit 5 = RxSPEED
bit 6 = RxPOWER
bit 7-11 = (reserved)
bit 12 = invert RXCLK
bit 13 = invert TXCLK
bit 14 = invert CLSN
bit 15 = invert CRS
bit 0 = Remote Cmd Done (sent)
bit 1 = Remote Cmd Valid (received)
bit 2 = Packet Transmitted
bit 3 = Packet Received
bit 4 = Home Link Status Change
bit 8 = TxPCOM Ready
bit 9 = RxPCOM Valid
bit 10-15 = software interrupts
20
Default
0x0004
0x0000
0x0000